[U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

[Marek Vasut]

On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
[...]
> >>> Hi,
> >>> 
> >>> yeah, I have some insane amount of cleanup patches and fixes already. I
> >>> will post them once I'm done. What I am sorely missing is the UniPHY
> >>> register interface documentation, it looks like that is not public, so
> >>> I don't exactly know if what sequencer.c does is really correct.
> >>> Sometimes I have serious doubts about that too . Can you give me the
> >>> documentation please ?
> >> 
> >> Have you seen this link[1]?
> > 
> > Yes, but that is by far not all of the registers used in the sequencer.c,
> > is it ?
> 
> Looks like it's in the entire emi.pdf file[1]. Please look at volume 3,
> or page 531 of 895. The section for the UniPHY.

I extracted all the possible addresses used in the sequencer while cleaning
it up, they're below. I cannot find these in any documentation. I checked the
EMI RM, sure, but there seems to be many more registers all around the place
than what are described in the EMI RM. Any ideas please ? Maybe this is not
even the UniPHY anymore ?

 19 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET          0x0
 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET            0x0400
 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET       0x1000
 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET       0x1400
 23 #define RW_MGR_INST_ROM_WRITE_OFFSET            0x1800
 24 #define RW_MGR_AC_ROM_WRITE_OFFSET              0x1C00
[...]
 80 #define SCC_MGR_GROUP_COUNTER_OFFSET            0x0000
 81 #define SCC_MGR_DQS_IN_DELAY_OFFSET             0x0100
 82 #define SCC_MGR_DQS_EN_PHASE_OFFSET             0x0200
 83 #define SCC_MGR_DQS_EN_DELAY_OFFSET             0x0300
 84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET          0x0400
 85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET           0x0500
 86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET            0x0700
 87 #define SCC_MGR_IO_IN_DELAY_OFFSET              0x0900
 88 
 89 /* HHP-HPS-specific versions of some commands */
 90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET        0x0600
 91 #define SCC_MGR_IO_OE_DELAY_OFFSET              0x0800
 92 #define SCC_MGR_HHP_GLOBALS_OFFSET              0x0A00
 93 #define SCC_MGR_HHP_RFILE_OFFSET                0x0B00
 94 #define SCC_MGR_AFI_CAL_INIT_OFFSET             0x0D00
 95 
 96 #define SDR_PHYGRP_SCCGRP_ADDRESS     (SOCFPGA_SDR_ADDRESS | 0x0)
 97 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS  (SOCFPGA_SDR_ADDRESS | 0x1000)
 98 #define SDR_PHYGRP_RWMGRGRP_ADDRESS   (SOCFPGA_SDR_ADDRESS | 0x2000)
 99 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
100 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)

Then there's this in sequencer.c , again after cleanup:

  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)
             (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19 
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)
             (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22 
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25 
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27     (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28 
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30     (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31 
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33     (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34 
  35 static struct socfpga_data_mgr *data_mgr =
  36     (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37 
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39     (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

> Dinh
> [1]
> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/
> hb/external-memory/emi.pdf

Best regards,
Marek Vasut