[U-Boot] [PATCH 03/15][v2] imx: mmc: fsl_esdhc fix dcache issue

[Adrian Alonso]

DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.

We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.

With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.

Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
Signed-off-by: Ye.Li <B37916 at freescale.com>
Signed-off-by: Nitin Garg <nitin.garg at freescale.com>
Signed-off-by: Jason Liu <r64343 at freescale.com>
Signed-off-by: Adrian Alonso <aalonso at freescale.com>
---
Changes for V2: Resend

 drivers/mmc/fsl_esdhc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c4719e6..0510bf0 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		err = esdhc_setup_data(mmc, data);
 		if(err)
 			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
 	}
 
 	/* Figure out the transfer arguments */
@@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 			}
 		} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
 
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
 		if (data->flags & MMC_DATA_READ)
 			check_and_invalidate_dcache_range(cmd, data);
 #endif
-- 
2.1.4