[U-Boot] [PATCH v3 3/7] x86: qemu: Enable I/O APIC chip select on PIIX3

[Bin Meng]

The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/qemu/pci.c               | 7 ++++++-
 arch/x86/include/asm/arch-qemu/qemu.h | 6 +++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index 1a9140b..ab93e76 100644
--- a/arch/x86/cpu/qemu/pci.c
+++ b/arch/x86/cpu/qemu/pci.c
@@ -50,7 +50,7 @@ void board_pci_setup_hose(struct pci_controller *hose)
 int board_pci_post_scan(struct pci_controller *hose)
 {
 	int ret = 0;
-	u16 device;
+	u16 device, xbcs;
 	int pam, i;
 	pci_dev_t vga;
 	ulong start;
@@ -82,6 +82,11 @@ int board_pci_post_scan(struct pci_controller *hose)
 		 */
 		x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
 		x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
+
+		/* Enable I/O APIC */
+		xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
+		xbcs |= APIC_EN;
+		x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
 	}
 
 	/*
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
index 5cbffff..8c8e4ac 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -13,10 +13,14 @@
 #define PAM_NUM			7
 #define PAM_RW			0x33
 
+/* X-Bus Chip Select Register */
+#define XBCS			0x4e
+#define APIC_EN			(1 << 8)
+
 /* IDE Timing Register */
 #define IDE0_TIM		0x40
 #define IDE1_TIM		0x42
-#define IDE_DECODE_EN		0x8000
+#define IDE_DECODE_EN		(1 << 15)
 
 /* I/O Ports */
 #define CMOS_ADDR_PORT		0x70
-- 
1.8.2.1