[U-Boot] [PATCH v3 7/7] x86: Reserve PCIe ECAM address range in the E820 table

[Bin Meng]

We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>

---

Changes in v3: None
Changes in v2:
- New patch to reserve PCIe ECAM address range in the E820 table

 arch/x86/Kconfig            | 10 ++++++++++
 arch/x86/lib/fsp/fsp_dram.c |  6 ++++++
 arch/x86/lib/zimage.c       |  5 ++++-
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index cbbaa4f..e8968a7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -369,4 +369,14 @@ config PCIE_ECAM_BASE
 	  assigned to PCI devices - i.e. the memory and prefetch regions, as
 	  passed to pci_set_region().
 
+config PCIE_ECAM_SIZE
+	hex
+	default 0x10000000
+	help
+	  This is the size of memory-mapped address of PCI configuration space,
+	  which is only available through the Enhanced Configuration Access
+	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
+	  so a default 0x10000000 size covers all of the 256 buses which is the
+	  maximum number of PCI buses as defined by the PCI specification.
+
 endmenu
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 4c0a7c8..28552fa 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -77,5 +77,11 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
 		num_entries++;
 	}
 
+	/* Mark PCIe ECAM address range as reserved */
+	entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[num_entries].type = E820_RESERVED;
+	num_entries++;
+
 	return num_entries;
 }
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 144471c..a1ec57e 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -61,8 +61,11 @@ __weak unsigned install_e820_map(unsigned max_entries,
 	entries[2].addr = ISA_END_ADDRESS;
 	entries[2].size = gd->ram_size - ISA_END_ADDRESS;
 	entries[2].type = E820_RAM;
+	entries[3].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[3].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[3].type = E820_RESERVED;
 
-	return 3;
+	return 4;
 }
 
 static void build_command_line(char *command_line, int auto_boot)
-- 
1.8.2.1