[U-Boot] [V4 2/2] sf: Turn SPI flash into 3-Byte address mode on Micron chips

[Zhiqiang Hou]

From: Hou Zhiqiang <B48286 at freescale.com>

For more than 16MiB Micron chips, there are 3-Byte and 4-Byte address mode,
and only the 3-Byte address mode is supported in u-boot.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may be in 4-Byte address mode after warm boot.

Signed-off-by: Hou Zhiqiang <B48286 at freescale.com>
---
 drivers/mtd/spi/sf_internal.h |  8 ++++++++
 drivers/mtd/spi/sf_ops.c      | 24 ++++++++++++++++++++++++
 drivers/mtd/spi/sf_probe.c    |  5 +++++
 3 files changed, 37 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 703d4a7..3d7ed24 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -75,6 +75,10 @@ enum {
 #define CMD_FLAG_STATUS			0x70
 #define CMD_CLEAR_FLAG_STATUS		0x50
 
+/* Used for Macronix and Winbond flashes */
+#define	CMD_ENTER_4B_ADDR		0xB7
+#define	CMD_EXIT_4B_ADDR		0xE9
+
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
 #define CMD_READ_ARRAY_FAST		0x0b
@@ -227,6 +231,10 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		size_t len, void *data);
 
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
 #ifdef CONFIG_SPI_FLASH_MTD
 int spi_flash_mtd_register(struct spi_flash *flash);
 void spi_flash_mtd_unregister(void);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index cbb9f00..1ce14d1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
 }
 #endif
 
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable)
+{
+	int ret;
+	u8 cmd;
+
+	cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+	ret = spi_claim_bus(flash->spi);
+	if (ret) {
+		debug("SF: unable to claim SPI bus\n");
+		return ret;
+	}
+
+	ret = spi_flash_cmd_write_enable(flash);
+	if (ret < 0) {
+		debug("SF: enabling write failed\n");
+		return ret;
+	}
+
+	return spi_flash_cmd(flash->spi, cmd, NULL, 0);
+}
+#endif
+
 #ifdef CONFIG_SPI_FLASH_BAR
 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
 {
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index e0283dc..5ba7dde 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -231,6 +231,11 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	if (params->flags & E_FSR)
 		flash->poll_cmd = CMD_FLAG_STATUS;
+
+	if (flash->size > SPI_FLASH_16MB_BOUN) {
+		if (spi_flash_cmd_4B_addr_switch(flash, 0) < 0)
+			debug("SF: enter 3B address mode failed\n");
+	}
 #endif
 
 	/* Configure the BAR - discover bank cmds and read current bank */
-- 
2.1.0.27.g96db324