[U-Boot] [PATCH v3 3/4] ARM: cache: implement a default weak flush_cache() function

[Josh Wu]

Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---

Changes in v3:
- new added.

 arch/arm/cpu/arm1136/cpu.c     |  9 ---------
 arch/arm/cpu/arm926ejs/cache.c |  9 ---------
 arch/arm/cpu/armv7/cache_v7.c  | 13 -------------
 arch/arm/cpu/armv8/cache_v8.c  |  8 --------
 arch/arm/lib/cache.c           | 26 +++++---------------------
 5 files changed, 5 insertions(+), 60 deletions(-)

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index b4d1d54..f092ffc 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -120,11 +120,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-void flush_cache(unsigned long start, unsigned long size)
-{
-	flush_dcache_range(start, start + size);
-}
-
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -133,10 +128,6 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 99d1a13..e5c1a6a 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -69,11 +69,6 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 
 	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-	flush_dcache_range(start, start + size);
-}
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -82,10 +77,6 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 /*
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 4f0e406..a5aa4fa 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -286,15 +286,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 	flush_dcache_range(start, stop);
 	v7_inval_tlb();
 }
-
-/*
- * Flush range from all levels of d-cache/unified-cache used:
- * Affects the range [start, start + size - 1]
- */
-void  flush_cache(unsigned long start, unsigned long size)
-{
-	flush_dcache_range(start, start + size);
-}
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -308,10 +299,6 @@ void arm_init_before_mmu(void)
 {
 }
 
-void  flush_cache(unsigned long start, unsigned long size)
-{
-}
-
 void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index f8c17cc..92b66c3 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -217,11 +217,3 @@ void __weak enable_caches(void)
 	icache_enable();
 	dcache_enable();
 }
-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
-	flush_dcache_range(start, start + size);
-}
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index bc48f53..cd13db3 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,29 +10,13 @@
 #include <common.h>
 #include <malloc.h>
 
+/*
+ * Flush range from all levels of d-cache/unified-cache.
+ * Affects the range [start, start + size - 1].
+ */
 __weak void flush_cache(unsigned long start, unsigned long size)
 {
-#if defined(CONFIG_CPU_ARM1136)
-
-#if !defined(CONFIG_SYS_ICACHE_OFF)
-	asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
-#endif
-
-#if !defined(CONFIG_SYS_DCACHE_OFF)
-	asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
-#endif
-
-#endif /* CONFIG_CPU_ARM1136 */
-
-#ifdef CONFIG_CPU_ARM926EJS
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-	/* test and clean, page 2-23 of arm926ejs manual */
-	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-	/* disable write buffer as well (page 2-22) */
-	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-#endif /* CONFIG_CPU_ARM926EJS */
-	return;
+	flush_dcache_range(start, start + size);
 }
 
 /*
-- 
1.9.1