[U-Boot] Please pull u-boot-x86
Simon Glass
sjg at chromium.org
Tue Jul 28 19:42:22 CEST 2015
Hi Tom,
Here are some more PCI driver model improvements and better interrupt
support on x86.
The following changes since commit 66d10c18bf2c34698362b6fe1891bcc6e8755243:
Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze
(2015-07-28 11:31:21 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git
for you to fetch changes up to 488d19cbcace0b87a2d08881eab7356088198903:
patman: add distutils based installer (2015-07-28 10:36:25 -0600)
----------------------------------------------------------------
Bin Meng (20):
x86: Display correct CS/EIP/EFLAGS when there is an error code
x86: Simplify architecture defined exception handling in irq_llsr()
x86: Change pci option rom area MTRR setting to cacheable
x86: Enable DM RTC support for all x86 boards
x86: pci: Assign pci irqs to all functions
x86: pci: Do not assign irq 0 to pci device
buildman: Correct '--fetch-arch' command documentation
Fix incorrect comments in linker_lists.h
dm: pci: Correct primary/secondary/subordinate bus number assignment
dm: pci: Use complete bdf in all pci config read/write routines
dm: pci: Pass only device/function to pci_bus_find_devfn()
dm: pci: Support bridge device configuration correctly
x86: Convert to use driver model pci on queensbay/crownbay
x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC
x86: mpspec: Move writing ISA interrupt entry after PCI
x86: qemu: Enable I/O APIC chip select on PIIX3
x86: Allow cpu-x86 driver to be probed for UP
x86: qemu: Enable writing MP table
x86: qemu: Turn on PCIe ECAM address range decoding on Q35
x86: Reserve PCIe ECAM address range in the E820 table
Chris Packham (1):
patman: add distutils based installer
arch/x86/Kconfig | 10 ++++
arch/x86/cpu/cpu.c | 36 ++++++++++++---
arch/x86/cpu/interrupts.c | 180
++++++++++++++++++++++++++++++------------------------------------------
arch/x86/cpu/ivybridge/lpc.c | 1 -
arch/x86/cpu/ivybridge/sdram.c | 32 +++++++++----
arch/x86/cpu/pci.c | 29 ++++++++----
arch/x86/cpu/qemu/pci.c | 45 ++++++++++++++++--
arch/x86/cpu/queensbay/Makefile | 1 -
arch/x86/cpu/queensbay/tnc.c | 5 --
arch/x86/cpu/queensbay/tnc_pci.c | 46 -------------------
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/chromebox_panther.dts | 1 +
arch/x86/dts/crownbay.dts | 6 ++-
arch/x86/dts/galileo.dts | 1 +
arch/x86/dts/minnowmax.dts | 1 +
arch/x86/dts/qemu-x86_i440fx.dts | 13 ++++++
arch/x86/dts/qemu-x86_q35.dts | 13 ++++++
arch/x86/dts/rtc.dtsi | 1 +
arch/x86/include/asm/arch-qemu/qemu.h | 10 +++-
arch/x86/include/asm/interrupt.h | 24 ++++++++++
arch/x86/include/asm/mpspec.h | 17 +++++++
arch/x86/include/asm/mtrr.h | 2 +
arch/x86/include/asm/pci.h | 3 +-
arch/x86/include/asm/ptrace.h | 16 +++++--
arch/x86/lib/fsp/fsp_dram.c | 6 +++
arch/x86/lib/mpspec.c | 50 +++++++++++++++-----
arch/x86/lib/pirq_routing.c | 3 +-
arch/x86/lib/zimage.c | 5 +-
configs/chromebook_link_defconfig | 1 +
configs/chromebox_panther_defconfig | 1 +
configs/crownbay_defconfig | 1 +
configs/galileo_defconfig | 1 +
configs/minnowmax_defconfig | 1 +
configs/qemu-x86_defconfig | 4 ++
drivers/pci/pci-uclass.c | 62 ++++++++++++-------------
drivers/pci/pci_auto.c | 75 +++++++++++++++++++++++++-----
drivers/pci/pci_common.c | 7 ++-
include/linker_lists.h | 20 ++++----
tools/buildman/README | 4 +-
tools/patman/README | 11 +++++
tools/patman/__init__.py | 3 ++
tools/patman/patman.py | 20 ++++----
tools/patman/setup.py | 13 ++++++
43 files changed, 506 insertions(+), 276 deletions(-)
delete mode 100644 arch/x86/cpu/queensbay/tnc_pci.c
create mode 100644 tools/patman/__init__.py
create mode 100644 tools/patman/setup.py
Regards,
Simon
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