[U-Boot] [PATCH 14/15] RFC: x86: minnowmax: Add interrupt routing setup

[Simon Glass]

Hi Bin,

On 28 July 2015 at 18:46, Bin Meng <bmeng.cn at gmail.com> wrote:
> Hi Simon,
>
> On Wed, Jul 29, 2015 at 8:42 AM, Simon Glass <sjg at chromium.org> wrote:
>> Hi Bin,
>>
>> On 28 July 2015 at 18:40, Bin Meng <bmeng.cn at gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Tue, Jul 28, 2015 at 7:58 PM, Simon Glass <sjg at chromium.org> wrote:
>>>> Hi Bin,
>>>>
>>>> On 28 July 2015 at 01:50, Bin Meng <bmeng.cn at gmail.com> wrote:
>>>>>
>>>>> Hi Simon,
>>>>>
>>>>> On Tue, Jul 28, 2015 at 5:47 AM, Simon Glass <sjg at chromium.org> wrote:
>>>>> > At present minnowmax does not correct set up PCI interrupts. This should be
>>>>> > done in U-Boot so that devices work correctly in Linux.
>>>>> >
>>>>> > Note: This code needs to make use of the recent pirq_routing work. It does
>>>>> > not seem to support all the required features, so this RFC will hopefully
>>>>>
>>>>> What features are missing in the existing PIRQ codes? When I did the
>>>>> PIRQ support, I checked both TunnelCreek and BayTrail chipset
>>>>> datasheet, and found the only difference seems to be the pci
>>>>> configuration space vs. memory-mapped IBASE where the pci irq routing
>>>>> registers reside.
>>>>
>>>> I see that each PCI device can be assigned four routes, making up a
>>>> 16-bit register. But the code I see in pirq_assign_req() only assigns
>>>> a single one, using a byte register.
>>>>
>>>
>>> No, the pci irq routing register is still a 8-bit register on
>>> BayTrail, where pirq_assign_irq() programs. The 16-bit register you
>>> mentioned should be done in the platform codes. See
>>> arch/x86/cpu/queensbay/tnc.c::cpu_irq_init(). By the way actually we
>>> can leave those register programmed as they have the optimized default
>>> values for all pci devices after power up, unless we intentionally
>>> want to change them.
>>
>> What do you mean by 'leave those register programmed'?
>>
>
> I mean their default value is normally OK, like INTA maps PIRQA, INTB
> maps PIRQB, INTC maps PIRQC and INTD maps PIRQD.

OK, so drop writing to the pirq registers?

Should I program the 16-bit registers? If so, I will need to extend
the device tree binding, won't I?

Sorry my understanding is limited on this - and I'd like to use your
generic code if possible.

Regards,
Simon