[U-Boot] [PATCH 7/7] x86: bayleybay: Configure PCI IRQ

Simon Glass sjg at chromium.org
Thu Jul 30 21:53:58 CEST 2015


Hi Bin,

On 30 July 2015 at 04:49, Bin Meng <bmeng.cn at gmail.com> wrote:
> Add PCI IRQ routing information in the board device tree and enable
> writing PIRQ routing table and MP table.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>
> ---
>
>  arch/x86/cpu/baytrail/valleyview.c |  8 +++++
>  arch/x86/dts/bayleybay.dts         | 63 ++++++++++++++++++++++++++++++++++++++
>  configs/bayleybay_defconfig        |  2 ++
>  include/configs/bayleybay.h        |  1 +
>  4 files changed, 74 insertions(+)
>
> diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
> index 9915da5..d8d2b8d 100644
> --- a/arch/x86/cpu/baytrail/valleyview.c
> +++ b/arch/x86/cpu/baytrail/valleyview.c
> @@ -7,6 +7,7 @@
>  #include <common.h>
>  #include <mmc.h>
>  #include <pci_ids.h>
> +#include <asm/irq.h>
>  #include <asm/post.h>
>
>  static struct pci_device_id mmc_supported[] = {
> @@ -35,3 +36,10 @@ int arch_cpu_init(void)
>
>         return 0;
>  }
> +
> +int arch_misc_init(void)
> +{
> +       pirq_init();
> +
> +       return 0;
> +}
> diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
> index cbbdee2..9f8fa70 100644
> --- a/arch/x86/dts/bayleybay.dts
> +++ b/arch/x86/dts/bayleybay.dts
> @@ -7,6 +7,7 @@
>  /dts-v1/;
>
>  #include <dt-bindings/gpio/x86-gpio.h>
> +#include <dt-bindings/interrupt-router/intel-irq.h>
>
>  /include/ "skeleton.dtsi"
>  /include/ "serial.dtsi"
> @@ -123,6 +124,68 @@
>                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
>                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
>                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
> +
> +               irq-router at 1f,0 {
> +                       reg = <0x0000f800 0 0 0 0>;
> +                       compatible = "intel,irq-router";
> +                       intel,pirq-config = "ibase";
> +                       intel,ibase-offset = <0x50>;
> +                       intel,pirq-link = <8 8>;
> +                       intel,pirq-mask = <0xdee0>;
> +                       intel,pirq-routing = <
> +                               /* BayTrail PCI devices */
> +                               PCI_BDF(0, 2, 0) INTA PIRQA
> +                               PCI_BDF(0, 3, 0) INTA PIRQA
> +                               PCI_BDF(0, 16, 0) INTA PIRQA
> +                               PCI_BDF(0, 17, 0) INTA PIRQA
> +                               PCI_BDF(0, 18, 0) INTA PIRQA
> +                               PCI_BDF(0, 19, 0) INTA PIRQA
> +                               PCI_BDF(0, 20, 0) INTA PIRQA
> +                               PCI_BDF(0, 21, 0) INTA PIRQA
> +                               PCI_BDF(0, 22, 0) INTA PIRQA
> +                               PCI_BDF(0, 23, 0) INTA PIRQA
> +                               PCI_BDF(0, 24, 0) INTA PIRQA
> +                               PCI_BDF(0, 24, 1) INTC PIRQC
> +                               PCI_BDF(0, 24, 2) INTD PIRQD
> +                               PCI_BDF(0, 24, 3) INTB PIRQB
> +                               PCI_BDF(0, 24, 4) INTA PIRQA
> +                               PCI_BDF(0, 24, 5) INTC PIRQC
> +                               PCI_BDF(0, 24, 6) INTD PIRQD
> +                               PCI_BDF(0, 24, 7) INTB PIRQB
> +                               PCI_BDF(0, 26, 0) INTA PIRQA
> +                               PCI_BDF(0, 27, 0) INTA PIRQA
> +                               PCI_BDF(0, 28, 0) INTA PIRQA
> +                               PCI_BDF(0, 28, 1) INTB PIRQB
> +                               PCI_BDF(0, 28, 2) INTC PIRQC
> +                               PCI_BDF(0, 28, 3) INTD PIRQD
> +                               PCI_BDF(0, 29, 0) INTA PIRQA
> +                               PCI_BDF(0, 30, 0) INTA PIRQA
> +                               PCI_BDF(0, 30, 1) INTD PIRQD
> +                               PCI_BDF(0, 30, 2) INTB PIRQB
> +                               PCI_BDF(0, 30, 3) INTC PIRQC
> +                               PCI_BDF(0, 30, 4) INTD PIRQD
> +                               PCI_BDF(0, 30, 5) INTB PIRQB
> +                               PCI_BDF(0, 31, 3) INTB PIRQB

I interested to understand how you come to these values? Are they in
the datasheet, or somewhere else?

Also it seems odd to specify the interrupts for each device here
instead of in the device node for each device. But of course most
devices won't have a node so this is our only option.

> +
> +                               /* PCIe root ports downstream interrupts */
> +                               PCI_BDF(1, 0, 0) INTA PIRQA
> +                               PCI_BDF(1, 0, 0) INTB PIRQB
> +                               PCI_BDF(1, 0, 0) INTC PIRQC
> +                               PCI_BDF(1, 0, 0) INTD PIRQD
> +                               PCI_BDF(2, 0, 0) INTA PIRQB
> +                               PCI_BDF(2, 0, 0) INTB PIRQC
> +                               PCI_BDF(2, 0, 0) INTC PIRQD
> +                               PCI_BDF(2, 0, 0) INTD PIRQA
> +                               PCI_BDF(3, 0, 0) INTA PIRQC
> +                               PCI_BDF(3, 0, 0) INTB PIRQD
> +                               PCI_BDF(3, 0, 0) INTC PIRQA
> +                               PCI_BDF(3, 0, 0) INTD PIRQB
> +                               PCI_BDF(4, 0, 0) INTA PIRQD
> +                               PCI_BDF(4, 0, 0) INTB PIRQA
> +                               PCI_BDF(4, 0, 0) INTC PIRQB
> +                               PCI_BDF(4, 0, 0) INTD PIRQC
> +                       >;
> +               };
>         };
>
>         microcode {
> diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
> index e10e86a..7f92ead 100644
> --- a/configs/bayleybay_defconfig
> +++ b/configs/bayleybay_defconfig
> @@ -5,6 +5,8 @@ CONFIG_TARGET_BAYLEYBAY=y
>  CONFIG_HAVE_INTEL_ME=y
>  CONFIG_SMP=y
>  CONFIG_HAVE_VGA_BIOS=y
> +CONFIG_GENERATE_PIRQ_TABLE=y
> +CONFIG_GENERATE_MP_TABLE=y
>  CONFIG_CMD_CPU=y
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
> diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
> index cc95aec..740166a 100644
> --- a/include/configs/bayleybay.h
> +++ b/include/configs/bayleybay.h
> @@ -14,6 +14,7 @@
>  #include <configs/x86-common.h>
>
>  #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
> +#define CONFIG_ARCH_MISC_INIT
>
>  #define CONFIG_X86_SERIAL
>
> --
> 1.8.2.1
>

Regards,
Simon


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