[U-Boot] [PATCH] imx: usb: ehci-mx6: add usb support for imx7d soc
Adrian Alonso
aalonso at freescale.com
Fri Jul 31 00:34:00 CEST 2015
Extend ehci-mx6 usb driver to support imx7d usb
Signed-off-by: Adrian Alonso <aalonso at freescale.com>
---
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-mx6.c | 125 ++++++++++++++++++++++++++++++++------------
2 files changed, 92 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6cc3bbd..8537b6b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
+obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 951dd3b..0ea19ec 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -45,7 +45,8 @@
#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
-
+#define USB_NC_OFFSET 0x200
+#define UCTRL_PM (1 << 9) /* OTG Power Mask */
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
@@ -53,6 +54,7 @@
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
+#if defined(CONFIG_MX6)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
@@ -67,7 +69,7 @@ static void usb_internal_phy_clock_gate(int index, int on)
phy_reg = (void __iomem *)phy_bases[index];
phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
- __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
+ writel(USBPHY_CTRL_CLKGATE, phy_reg);
}
static void usb_power_config(int index)
@@ -100,14 +102,14 @@ static void usb_power_config(int index)
* is totally controlled by IC, so the Software only needs
* to enable them at initializtion.
*/
- __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+ writel(ANADIG_USB2_CHRG_DETECT_EN_B |
ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
chrg_detect);
- __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+ writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
pll_480_ctrl_clr);
- __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+ writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
ANADIG_USB2_PLL_480_CTRL_POWER |
ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
pll_480_ctrl_set);
@@ -119,7 +121,6 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
void __iomem *phy_reg;
void __iomem *phy_ctrl;
void __iomem *usb_cmd;
- u32 val;
if (index >= ARRAY_SIZE(phy_bases))
return 0;
@@ -129,36 +130,27 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
usb_cmd = (void __iomem *)&ehci->usbcmd;
/* Stop then Reset */
- val = __raw_readl(usb_cmd);
- val &= ~UCMD_RUN_STOP;
- __raw_writel(val, usb_cmd);
- while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
+ clrbits_le32(usb_cmd, UCMD_RUN_STOP);
+ while (readl(usb_cmd) & UCMD_RUN_STOP)
;
- val = __raw_readl(usb_cmd);
- val |= UCMD_RESET;
- __raw_writel(val, usb_cmd);
- while (__raw_readl(usb_cmd) & UCMD_RESET)
+ setbits_le32(usb_cmd, UCMD_RESET);
+ while (readl(usb_cmd) & UCMD_RESET)
;
/* Reset USBPHY module */
- val = __raw_readl(phy_ctrl);
- val |= USBPHY_CTRL_SFTRST;
- __raw_writel(val, phy_ctrl);
+ setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
udelay(10);
/* Remove CLKGATE and SFTRST */
- val = __raw_readl(phy_ctrl);
- val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
- __raw_writel(val, phy_ctrl);
+ clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
udelay(10);
/* Power up the PHY */
- __raw_writel(0, phy_reg + USBPHY_PWD);
+ writel(0, phy_reg + USBPHY_PWD);
/* enable FS/LS device */
- val = __raw_readl(phy_ctrl);
- val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
- __raw_writel(val, phy_ctrl);
+ setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
+ USBPHY_CTRL_ENUTMILEVEL3);
return 0;
}
@@ -171,28 +163,46 @@ struct usbnc_regs {
u32 otg_phy_ctrl_0;
u32 uh1_phy_ctrl_0;
};
+#elif defined(CONFIG_MX7)
+struct usbnc_regs {
+ u32 ctrl1;
+ u32 ctrl2;
+ u32 reserve1[11];
+ u32 phy_ctrl2;
+ u32 reserve2[6];
+ u32 adp_cfg1;
+ u32 reserve3;
+ u32 adp_status;
+};
+#endif
static void usb_oc_config(int index)
{
+#if defined(CONFIG_MX6)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
- u32 val;
+#elif defined(CONFIG_MX7)
+ struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+ (0x10000 * index) + USB_NC_OFFSET);
+ void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
+#endif
- val = __raw_readl(ctrl);
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
/* mx6qarm2 seems to required a different setting*/
- val &= ~UCTRL_OVER_CUR_POL;
+ clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#else
- val |= UCTRL_OVER_CUR_POL;
+ setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif
- __raw_writel(val, ctrl);
- val = __raw_readl(ctrl);
- val |= UCTRL_OVER_CUR_DIS;
- __raw_writel(val, ctrl);
+#if defined(CONFIG_MX6)
+ setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+#elif defined(CONFIG_MX7)
+ setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
+#endif
}
+#if defined(CONFIG_MX6)
int usb_phy_mode(int port)
{
void __iomem *phy_reg;
@@ -202,7 +212,7 @@ int usb_phy_mode(int port)
phy_reg = (void __iomem *)phy_bases[port];
phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
- val = __raw_readl(phy_ctrl);
+ val = readl(phy_ctrl);
if (val & USBPHY_CTRL_OTG_ID)
return USB_INIT_DEVICE;
@@ -210,16 +220,48 @@ int usb_phy_mode(int port)
return USB_INIT_HOST;
}
+/*
+ * board_ehci_hcd_init - override usb phy mode
+ * @port: usb host/otg port
+ *
+ * Target board specific, override usb_phy_mode.
+ * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
+ * left disconnected in this case usb_phy_mode will not be able to identify
+ * the phy mode that usb port is used.
+ * Machine file overrides board_usb_phy_mode.
+ *
+ * Return: USB_INIT_DEVICE or USB_INIT_HOST
+ */
int __weak board_usb_phy_mode(int port)
{
return usb_phy_mode(port);
}
+#endif
+/*
+ * board_ehci_hcd_init - set usb vbus voltage
+ * @port: usb otg port
+ *
+ * Target board specific, setup iomux pad to setup supply vbus voltage
+ * for usb otg port. Machine board file overrides board_ehci_hcd_init
+ *
+ * Return: 0 Success
+ */
int __weak board_ehci_hcd_init(int port)
{
return 0;
}
+/*
+ * board_ehci_power - enables/disables usb vbus voltage
+ * @port: usb otg port
+ * @on: on/off vbus voltage
+ *
+ * Enables/disables supply vbus voltage for usb otg port.
+ * Machine board file overrides board_ehci_power
+ *
+ * Return: 0 Success
+ */
int __weak board_ehci_power(int port, int on)
{
return 0;
@@ -228,9 +270,14 @@ int __weak board_ehci_power(int port, int on)
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
+#if defined(CONFIG_MX6)
enum usb_init_type type;
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
(0x200 * index));
+#elif defined(CONFIG_MX7)
+ struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
+ (0x10000 * index));
+#endif
if (index > 3)
return -EINVAL;
@@ -240,24 +287,34 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* Do board specific initialization */
board_ehci_hcd_init(index);
+#if defined(CONFIG_MX6)
usb_power_config(index);
+#endif
usb_oc_config(index);
+#if defined(CONFIG_MX6)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
type = board_usb_phy_mode(index);
+#endif
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+#if defined(CONFIG_MX6)
if ((type == init) || (type == USB_INIT_DEVICE))
board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
if (type != init)
return -ENODEV;
if (type == USB_INIT_DEVICE)
return 0;
+#elif defined(CONFIG_MX7)
+ board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1);
+ if (init == USB_INIT_DEVICE)
+ return 0;
+#endif
setbits_le32(&ehci->usbmode, CM_HOST);
- __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+ writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mdelay(10);
--
2.1.4
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