[U-Boot] [PATCH 11/13][v4] imx: imx7d: add timer support for imx7d

[Adrian Alonso]

* Add timer support for imx7d SoC

Signed-off-by: Adrian Alonso <aalonso at freescale.com>
---
Changes for V2: Split from patch imx: imx7d: initial arch level support
Changes for V3: Resend
Changes for V4: Resend

 arch/arm/imx-common/timer.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index c12556a..bc4a673 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -49,6 +49,8 @@ static inline int gpt_has_clk_source_osc(void)
 		return 1;
 
 	return 0;
+#elif defined(CONFIG_MX7)
+	return 1;
 #else
 	return 0;
 #endif
@@ -56,6 +58,9 @@ static inline int gpt_has_clk_source_osc(void)
 
 static inline ulong gpt_get_clk(void)
 {
+#if defined(CONFIG_MX7)
+	return MXC_HCLK >> 3;
+#else
 #ifdef CONFIG_MXC_GPT_HCLK
 	if (gpt_has_clk_source_osc())
 		return MXC_HCLK >> 3;
@@ -64,6 +69,7 @@ static inline ulong gpt_get_clk(void)
 #else
 	return MXC_CLK32;
 #endif
+#endif
 }
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -106,7 +112,8 @@ int timer_init(void)
 		/* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
 		if (is_cpu_type(MXC_CPU_MX6DL) ||
 		    is_cpu_type(MXC_CPU_MX6SOLO) ||
-		    is_cpu_type(MXC_CPU_MX6SX)) {
+		    is_cpu_type(MXC_CPU_MX6SX) ||
+		    is_cpu_type(MXC_CPU_MX7D)) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */
-- 
2.1.4