[U-Boot] patch - arm - define SYS_CACHELINE_SIZE for mx5

[Fabio Estevam]

On Tue, Jun 2, 2015 at 8:31 PM, Chris Kuethe <chris.kuethe at gmail.com> wrote:
> mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for
> adding gadget support to usbarmory, but it's a property common the the
> entire SoC family - may as well make it available to all MX5 boards
>
> Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too
>
> Signed-off-by: Chris Kuethe <chris.kuethe at gmail.com>
> Cc: Tom Rini <trini at konsulko.com>
> Cc: Matthew Starr <mstarr at hedonline.com>
> Cc: Andrej Rosano <andrej at inversepath.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Chris Kuethe <chris.kuethe at gmail.com>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Marek Vasut <marex at denx.de>
>
> diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
> b/arch/arm/include/asm/arch-mx5/imx-regs.h
> index f059d0f..5f0e1e6 100644
> --- a/arch/arm/include/asm/arch-mx5/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
> @@ -9,6 +9,8 @@
>
>  #define ARCH_MXC
>
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +

This is correct for Cortex A8:

Reviewed-by: Fabio Estevam <fabio.estevam at freescale.com>