[U-Boot] [PATCH v3 02/15] tegra: spi: Drop the claim_bus() method to correct delays

[Simon Glass]

At present the driver does not properly honour the requested SPI CS
deactivation delay since the SPI bus is changed in the claim_bus() method.

Everything the claim_bus() method does can be done when the device is probed
(setting the speed and mode) and at the start of a new transfer (where the
fifo_status is already cleared). So drop this method.

Also, until the delay is complete, we should not touch the bus, so make sure
that spi_cs_activate() is called before other things are done in the xfer()
method.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3: None
Changes in v2: None

 drivers/spi/tegra114_spi.c | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 4bec663..0d69376 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -143,24 +143,18 @@ static int tegra114_spi_probe(struct udevice *bus)
 {
 	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
 	struct tegra114_spi_priv *priv = dev_get_priv(bus);
+	struct spi_regs *regs;
 
 	priv->regs = (struct spi_regs *)plat->base;
+	regs = priv->regs;
 
 	priv->last_transaction_us = timer_get_us();
 	priv->freq = plat->frequency;
 	priv->periph_id = plat->periph_id;
 
-	return 0;
-}
-
-static int tegra114_spi_claim_bus(struct udevice *dev)
-{
-	struct udevice *bus = dev->parent;
-	struct tegra114_spi_priv *priv = dev_get_priv(bus);
-	struct spi_regs *regs = priv->regs;
-
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+			       priv->freq);
 
 	/* Clear stale status here */
 	setbits_le32(&regs->fifo_status,
@@ -175,9 +169,8 @@ static int tegra114_spi_claim_bus(struct udevice *dev)
 		     SPI_FIFO_STS_RX_FIFO_EMPTY);
 	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
 
-	/* Set master mode and sw controlled CS */
-	setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
-		     (priv->mode << SPI_CMD1_MODE_SHIFT));
+	setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
+		     (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
 	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
 
 	return 0;
@@ -249,6 +242,9 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 	ret = 0;
 
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(dev);
+
 	/* clear all error status bits */
 	reg = readl(&regs->fifo_status);
 	writel(reg, &regs->fifo_status);
@@ -260,9 +256,6 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	/* set xfer size to 1 block (32 bits) */
 	writel(0, &regs->dma_blk);
 
-	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(dev);
-
 	/* handle data in 32-bit chunks */
 	while (num_bytes > 0) {
 		int bytes;
@@ -385,7 +378,6 @@ static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
 }
 
 static const struct dm_spi_ops tegra114_spi_ops = {
-	.claim_bus	= tegra114_spi_claim_bus,
 	.xfer		= tegra114_spi_xfer,
 	.set_speed	= tegra114_spi_set_speed,
 	.set_mode	= tegra114_spi_set_mode,
-- 
2.2.0.rc0.207.ga3a616c