[U-Boot] [PATCH] arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoM
Markus Niebel
list-09_u-boot at tqsc.de
Mon Jun 15 15:29:22 CEST 2015
Hallo Stefan,
Am 15.06.2015 um 13:48 schrieb Stefan Roese:
> This patch adds support for the "OHB System AG" baseboard
> with is equipped with the TQMa6S SoM.
>
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Markus Niebel <Markus.Niebel at tq-group.com>
> Cc: Stefano Babic <sbabic at denx.de>
> ---
> board/tqc/tqma6/Makefile | 1 +
> board/tqc/tqma6/tqma6_wru4.c | 352 ++++++++++++++++++++++++++++++++++++++
> configs/tqma6s_wru4_mmc_defconfig | 10 ++
> include/configs/tqma6.h | 2 +
> include/configs/tqma6_wru4.h | 71 ++++++++
> 5 files changed, 436 insertions(+)
> create mode 100644 board/tqc/tqma6/tqma6_wru4.c
> create mode 100644 configs/tqma6s_wru4_mmc_defconfig
> create mode 100644 include/configs/tqma6_wru4.h
>
> diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile
> index 9ee6920..19b56d0 100644
> --- a/board/tqc/tqma6/Makefile
> +++ b/board/tqc/tqma6/Makefile
> @@ -7,3 +7,4 @@
> obj-y := tqma6.o
>
> obj-$(CONFIG_MBA6) += tqma6_mba6.o
> +obj-$(CONFIG_WRU4) += tqma6_wru4.o
> diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
> new file mode 100644
> index 0000000..1f47e8c
> --- /dev/null
> +++ b/board/tqc/tqma6/tqma6_wru4.c
> @@ -0,0 +1,352 @@
> +/*
> + * Copyright (C) 2012 Freescale Semiconductor, Inc.
> + * Author: Fabio Estevam <fabio.estevam at freescale.com>
> + *
> + * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
> + * Author: Markus Niebel <markus.niebel at tq-group.com>
> + *
> + * Copyright (C) 2015 Stefan Roese <sr at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/boot_mode.h>
> +#include <asm/imx-common/mxc_i2c.h>
> +
> +#include <common.h>
> +#include <fsl_esdhc.h>
> +#include <libfdt.h>
> +#include <malloc.h>
> +#include <i2c.h>
> +#include <micrel.h>
> +#include <miiphy.h>
> +#include <mmc.h>
> +#include <netdev.h>
> +
> +#include "tqma6_bb.h"
> +
> +/* UART */
> +#define UART4_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_PUE | \
> + PAD_CTL_PKE | \
> + PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_SLOW \
> + )
> +
> +static iomux_v3_cfg_t const uart4_pads[] = {
> + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
> +};
> +
> +static void setup_iomuxc_uart4(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
> +}
> +
> +/* MMC */
> +#define USDHC2_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_80ohm | \
> + PAD_CTL_SRE_FAST \
> + )
> +
> +#define USDHC2_CLK_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_47K_UP | \
> + PAD_CTL_SPEED_LOW | \
> + PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_FAST \
> + )
> +
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
> +
> + NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
> + NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
> +#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
> +
> +static struct fsl_esdhc_cfg usdhc2_cfg = {
> + .esdhc_base = USDHC2_BASE_ADDR,
> + .max_bus_width = 4,
> +};
> +
> +int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + if (cfg->esdhc_base == USDHC2_BASE_ADDR)
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> +
> + return ret;
> +}
> +
> +int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + if (cfg->esdhc_base == USDHC2_BASE_ADDR)
> + ret = gpio_get_value(USDHC2_WP_GPIO);
> +
> + return ret;
> +}
> +
> +int tqma6_bb_board_mmc_init(bd_t *bis)
> +{
> + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> + gpio_direction_input(USDHC2_CD_GPIO);
> + gpio_direction_input(USDHC2_WP_GPIO);
> +
> + usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
> + puts("WARNING: failed to initialize SD\n");
> +
> + return 0;
> +}
> +
> +/* Ethernet */
> +#define ENET_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_PUE | \
> + PAD_CTL_PKE | \
> + PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_SLOW \
> + )
> +
> +static iomux_v3_cfg_t const enet_pads[] = {
> + NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
> + NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
> +
> + /* ENET1 reset */
> + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
> + /* ENET1 interrupt */
> + NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
> +};
> +
> +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
> +
> +static void setup_iomuxc_enet(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> +
> + /* Reset LAN8720 PHY */
> + gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
> + udelay(1000);
> + gpio_set_value(ENET_PHY_RESET_GPIO, 1);
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + uint32_t base = IMX_FEC_BASE;
> + struct mii_dev *bus = NULL;
> + struct phy_device *phydev = NULL;
> + int ret;
> +
> + bus = fec_get_miibus(base, -1);
> + if (!bus) {
> + puts("MII bus not found\n");
> + return 0;
> + }
> +
> + /* scan phy */
> + phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
> + PHY_INTERFACE_MODE_RMII);
> + if (!phydev) {
> + free(bus);
> + puts("No phy found\n");
> + return 0;
> + }
> +
> + ret = fec_probe(bis, -1, base, bus, phydev);
> + if (ret) {
> + puts("FEC MXC: probe failed\n");
> + free(phydev);
> + free(bus);
> + }
> +
> + return 0;
> +}
This was implemented in the original starter kit code to implement
the phy specific setup in board_phy_config. Your phy should not need
this.
> +
> +/* GPIO */
> +#define GPIO_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_PUE | \
> + PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_SLOW \
> + )
> +
> +#define GPIO_OD_PAD_CTRL ( \
> + PAD_CTL_HYS | \
> + PAD_CTL_PUS_100K_UP | \
> + PAD_CTL_PUE | \
> + PAD_CTL_ODE | \
> + PAD_CTL_SPEED_MED | \
> + PAD_CTL_DSE_40ohm | \
> + PAD_CTL_SRE_SLOW \
> + )
> +
> +static iomux_v3_cfg_t const gpio_pads[] = {
> + /* USB_H_PWR */
> + NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
> + /* USB_OTG_PWR */
> + NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
> + /* ENET1_RST */
> + NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, GPIO_PAD_CTRL),
This GPIO is already initialized in setup_iomuxc_enet.
> + /* PCIE_RST */
> + NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
> + /* UART1_PWRON */
> + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
> + /* UART2_PWRON */
> + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
> + /* UART3_PWRON */
> + NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
> +};
> +
> +#define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
> +#define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
> +#define GPIO_ENET1_RST IMX_GPIO_NR(1, 8)
> +#define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
> +#define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
> +#define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
> +#define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
> +
> +static void gpio_init(void)
> +{
> + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
> +
> + gpio_direction_output(GPIO_USB_H_PWR, 1);
> + gpio_direction_output(GPIO_USB_OTG_PWR, 1);
> + gpio_direction_output(GPIO_ENET1_RST, 1);
> + gpio_direction_output(GPIO_PCIE_RST, 1);
> + gpio_direction_output(GPIO_UART1_PWRON, 0);
> + gpio_direction_output(GPIO_UART2_PWRON, 0);
> + gpio_direction_output(GPIO_UART3_PWRON, 0);
Some GPIO (USB) are requested later in USB specific code. I would prefer
requesting all used GPIO - then the transition to DM_GPIO would be prepared
already.
> +}
> +
> +void tqma6_iomuxc_spi(void)
> +{
> + /* No SPI on this baseboard */
> +}
> +
> +int tqma6_bb_board_early_init_f(void)
> +{
> + setup_iomuxc_uart4();
> +
> + return 0;
> +}
> +
> +int tqma6_bb_board_init(void)
> +{
> + setup_iomuxc_enet();
> +
> + gpio_init();
> +
> + /* Turn the UART-couplers on one-after-another */
> + gpio_set_value(GPIO_UART1_PWRON, 1);
> + mdelay(10);
> + gpio_set_value(GPIO_UART2_PWRON, 1);
> + mdelay(10);
> + gpio_set_value(GPIO_UART3_PWRON, 1);
> +
> + return 0;
> +}
> +
> +int tqma6_bb_board_late_init(void)
> +{
> + return 0;
> +}
> +
> +const char *tqma6_bb_get_boardname(void)
> +{
> + return "WRU-IV";
> +}
> +
> +static const struct boot_mode board_boot_modes[] = {
> + /* 4 bit bus width */
> + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + /* 8 bit bus width */
> + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
> + { NULL, 0 },
> +};
> +
> +int misc_init_r(void)
> +{
> + add_board_boot_modes(board_boot_modes);
> +
> + return 0;
> +}
> +
> +#define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
> +#define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
> +
> +int board_ehci_hcd_init(int port)
> +{
> + int ret;
> +
> + ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
> + if (!ret)
> + gpio_direction_output(WRU4_USB_H1_PWR, 1);
> +
> + ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
> + if (!ret)
> + gpio_direction_output(WRU4_USB_OTG_PWR, 1);
> +
> + return 0;
> +}
> +
> +int board_ehci_power(int port, int on)
> +{
> + if (port)
> + gpio_set_value(WRU4_USB_OTG_PWR, on);
> + else
> + gpio_set_value(WRU4_USB_H1_PWR, on);
> +
> + return 0;
> +}
> +
> +/*
> + * Device Tree Support
> + */
> +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
> +void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
> +{
> + /* TBD */
> +}
> +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
> diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
> new file mode 100644
> index 0000000..74bca0b
> --- /dev/null
> +++ b/configs/tqma6s_wru4_mmc_defconfig
> @@ -0,0 +1,10 @@
> +CONFIG_ARM=y
> +CONFIG_TARGET_TQMA6=y
> +CONFIG_CMD_SETEXPR=y
> +CONFIG_CMD_NET=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/tqc/tqma6/tqma6s.cfg,MX6S,WRU4,TQMA6X_MMC_BOOT"
> +CONFIG_AUTOBOOT_KEYED=y
> +CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n"
> +CONFIG_AUTOBOOT_ENCRYPTION=y
> +CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
> +CONFIG_PCA9551_LED=y
Did you notice the patches for TQMa6 related config rework?
(arm: imx6: tqma6: Kconfig rework from 2015/06/04)
> diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
> index 00294f6..f807d08 100644
> --- a/include/configs/tqma6.h
> +++ b/include/configs/tqma6.h
> @@ -394,6 +394,8 @@
> */
> #ifdef CONFIG_MBA6
> #include "tqma6_mba6.h"
> +#elif CONFIG_WRU4
> +#include "tqma6_wru4.h"
> #else
> #error "No baseboard for the TQMa6 defined!"
> #endif
> diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
> new file mode 100644
> index 0000000..1c86bc0
> --- /dev/null
> +++ b/include/configs/tqma6_wru4.h
> @@ -0,0 +1,71 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr at denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_TQMA6_WRU4_H
> +#define __CONFIG_TQMA6_WRU4_H
> +
> +#define CONFIG_DEFAULT_FDT_FILE "imx6s-wru4.dtb"
> +
> +/* DTT sensors */
> +#define CONFIG_DTT_SENSORS { 0, 1 }
> +#define CONFIG_SYS_DTT_BUS_NUM 2
> +
> +/* Ethernet */
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC_PHYADDR 0x01
> +#define CONFIG_PHY_SMSC
> +
> +/* UART */
> +#define CONFIG_MXC_UART_BASE UART4_BASE
> +#define CONFIG_CONSOLE_DEV "ttymxc3"
> +
> +#define CONFIG_MISC_INIT_R
> +
> +/* Watchdog */
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_IMX_WATCHDOG
> +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
> +
> +/* Config on-board RTC */
> +#define CONFIG_RTC_DS1337
> +#define CONFIG_SYS_RTC_BUS_NUM 2
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
> +/* Turn off RTC square-wave output to save battery */
> +#define CONFIG_SYS_RTC_DS1337_NOOSC
> +#define CONFIG_CMD_DATE
> +
> +#define CONFIG_CMD_GPIO
> +
> +/* LED */
> +#define CONFIG_CMD_LED
> +#define CONFIG_STATUS_LED
> +#define CONFIG_BOARD_SPECIFIC_LED
> +#define STATUS_LED_BIT 0
> +#define STATUS_LED_STATE STATUS_LED_ON
> +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
> +#define STATUS_LED_BIT1 1
> +#define STATUS_LED_STATE1 STATUS_LED_ON
> +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
> +#define STATUS_LED_BIT2 2
> +#define STATUS_LED_STATE2 STATUS_LED_ON
> +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
> +#define STATUS_LED_BIT3 3
> +#define STATUS_LED_STATE3 STATUS_LED_ON
> +#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
> +#define STATUS_LED_BIT4 4
> +#define STATUS_LED_STATE4 STATUS_LED_ON
> +#define STATUS_LED_PERIOD4 (CONFIG_SYS_HZ / 2)
> +#define STATUS_LED_BIT5 5
> +#define STATUS_LED_STATE5 STATUS_LED_ON
> +#define STATUS_LED_PERIOD5 (CONFIG_SYS_HZ / 2)
> +
> +/* Bootcounter */
> +#define CONFIG_BOOTCOUNT_LIMIT
> +#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR
> +#define CONFIG_SYS_BOOTCOUNT_BE
> +
> +#endif /* __CONFIG_TQMA6_WRU4_H */
>
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