[U-Boot] x86: ACPI support suggestion

[Bin Meng]

Hi Gabriel,

On Sat, Feb 7, 2015 at 11:07 PM, Gabriel Huau <contact at huau-gabriel.fr> wrote:
> Hi Simon,
>
>
> On 02/06/2015 03:14 PM, Simon Glass wrote:
>>
>> Hi,
>>
>> On 6 February 2015 at 16:11, Gabriel Huau <contact at huau-gabriel.fr> wrote:
>>>
>>> Hi Simon,
>>>
>>>
>>> On 02/06/2015 03:04 PM, Simon Glass wrote:
>>>>
>>>> Hi Gabriel,
>>>>
>>>> On 6 February 2015 at 16:01, Gabriel Huau <contact at huau-gabriel.fr>
>>>> wrote:
>>>>>
>>>>> Hi Bin,
>>>>>
>>>>> Actually I was able to try with a quick&dirty code the integration of
>>>>> the
>>>>> ACPI tables (aml files) and it doesn't seem to be possible.
>>>>> The boot to Linux is working fine, all the ACPI tables are loaded
>>>>> correctly,
>>>>> but the system is unstable and it seems to have some issue with the
>>>>> interrupts handler.
>>>>>
>>>>> As debugging this kind of issues could be really tricky and involve
>>>>> also
>>>>> a
>>>>> lot of modification, I think we are stuck to port the ACPI support from
>>>>> coreboot to u-boot.
>>>>>
>>>>> I will try to work on a first draft and see how things look like.
>>>>
>>>> One thing to note is that U-Boot may not currently set up the PCI
>>>> interrupts fully. Or perhaps the problem is that ACPI needs to match.
>>>> What platform are you using?
>>>>
>>>> [snip]
>>>
>>>
>>> MinnowBoard Max (BayTrail).
>>>
>>> Actually, you may be right, I didn't check this part.
>>>
>> Actually that uses an FSP so might already be correct, but it is
>> certainly worth checking.
>
>
> I just checked the dmesg again and I didn't see that the first time:
>
> [    0.723098] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15)
> *0, disabled.
> [    0.732328] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 11 12 14 15)
> *0, disabled.
> [    0.741551] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15)
> *0, disabled.
> [    0.750782] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 11 12 14 15)
> *0, disabled.
> [    0.760006] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15)
> *0, disabled.
>
> So I believe the PIRQ routing is missing in u-boot. I checked in the source
> of Coreboot, and actually everything is done in the southcluster
> initialization.
> Also, I saw that the GPIO iomap wasn't done and it appeared that the USB2
> port wasn't powered up (the white one), enabling the port allow us to use of
> both port in the EHCI mode.
>
> I'll give a try to initialize the PIRQ and see how things is going.
>

Did you manage to get PIRQ work on MinnowMax? If not, I think you may
try to implement PIRQ routing support first to see how things go. You
can look at Intel Crown Bay device tree to add the PIRQ routing for
MinnowMax.

As for ACPI support, we have already started the work as part of GSoC 2015.

Regards,
Bin