[U-Boot] [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect rd-writes

[Graham Moore]

On 06/22/2015 06:31 PM, Vikas MANOCHA wrote:
...

>>> The point is if after applying above mentioned patch (...: fix
>>> indirect read/write start address), Read/write are working fine, then
>>> trigger_base value of 0xFFA00_0000 should also work fine.
>>> Can you please modify the trigger_base value from 0x0 to 0xFFA0_0000
>>> in Socfpga.dtsi & check.
>>> If it works, it would mean both (socfpga & stv0991) are behaving same.
>>
>> No. With this change, the "sf read" command crashes / hangs on the
>> SoCFPGA board.
>
> Ok, I don't know why socfpga is not working with trigger_base to be 0xFFA0_0000.
> Normally it should work, Graham also thinks the same, Let's wait for his discussion with the Altera designers.
>

Wait a minute, on SoCFPGA, the flashbase is 0xffa00000, and the trigger 
base is 0x00000000.  The point of having a different address was that 
they needed to be different on SoCFPGA, right?

As for why they're different, the Altera Cyclone5 SoCFPGA has a complex 
multilevel interconnect where the QSPI is three levels down, and is the 
only slave of an AHB master.  At that level of the interconnect, the 
base address has long been stripped off, it was used to select down to 
the final master.  The QSPI is the only thing on that AHB bus, so its 
address is zero.  Or at least that's how I understand it.

-Graham