[U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width

[Vikas MANOCHA]

Thanks Stefan,
Adding Jagan to apply the patchset.
Rgds,
Vikas

> -----Original Message-----
> From: Stefan Roese [mailto:sr at denx.de]
> Sent: Wednesday, June 24, 2015 3:09 AM
> To: Vikas MANOCHA
> Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com;
> dinguyen at opensource.altera.com
> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for
> FIFO width
> 
> Hi Vikas,
> 
> On 23.06.2015 16:48, Vikas MANOCHA wrote:
> >> -----Original Message-----
> >> From: Stefan Roese [mailto:sr at denx.de]
> >> Sent: Friday, June 12, 2015 5:10 AM
> >> To: Vikas MANOCHA; u-boot at lists.denx.de;
> >> grmoore at opensource.altera.com; dinguyen at opensource.altera.com
> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix
> >> for FIFO width
> >>
> >> Hi Vikas,
> >>
> >> On 11.06.2015 21:16, Vikas MANOCHA wrote:
> >>> Any comments on the patchset.
> >>
> >> I'll test them next week on a SoCFPGA based board and will comment
> >> then again.
> >
> > Can you please test this patchset also.
> 
> Okay. I've now tested this 3 patch series as well on top of mainline.
> And SPI NOR seems to work just fine with this one applied. Not errors and
> the write/read/compare test also works okay.
> 
> HTP.
> 
> Thanks,
> Stefan