[U-Boot] [PATCH v4] armv8: caches: Added routine to set non cacheable region

[Siva Durga Prasad Paladugu]

Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.

Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
Acked-by: Michal Simek <michal.simek at xilinx.com>
---
Changes for v4:
- Added DSB and ISB's as per review comment
Changes in v3:
- Removed board depenedency to calculate the page table
  address to start with looking into the entry. Now, get
  the page table address from the board specific code.
- Updated flush dcache with actual Page address instead
  of MMU entry.
Changes in v2:
- Fix patch subject (remove addional zzz from v1)
- Remove armv8: caches: Disable dcache after flush patch from this
  series based on the talk with Mark Rutland (patch is not needed
  anymore)
---
 arch/arm/cpu/armv8/cache_v8.c |   36 ++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/system.h |   29 +++++++++++++++++++----------
 2 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c5ec529..bddcdf7 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -139,6 +139,37 @@ int dcache_status(void)
 	return (get_sctlr() & CR_C) != 0;
 }
 
+u64 *__weak arch_get_page_table(void) {
+	puts("No page table offset defined\n");
+
+	return NULL;
+}
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	u64 *page_table = arch_get_page_table();
+	u64 upto, end;
+
+	if (page_table == NULL)
+		return;
+
+	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+	      MMU_SECTION_SHIFT;
+	start = start >> MMU_SECTION_SHIFT;
+	for (upto = start; upto < end; upto++) {
+		page_table[upto] &= ~PMD_ATTRINDX_MASK;
+		page_table[upto] |= PMD_ATTRINDX(option);
+	}
+	asm volatile("dsb sy");
+	__asm_invalidate_tlb_all();
+	asm volatile("dsb sy");
+	asm volatile("isb");
+	start = start << MMU_SECTION_SHIFT;
+	end = end << MMU_SECTION_SHIFT;
+	flush_dcache_range(start, end);
+	asm volatile("dsb sy");
+}
 #else	/* CONFIG_SYS_DCACHE_OFF */
 
 void invalidate_dcache_all(void)
@@ -170,6 +201,11 @@ int dcache_status(void)
 	return 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+}
+
 #endif	/* CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 760e8ab..868ea54 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -15,9 +15,15 @@
 #define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
 
 #define PGTABLE_SIZE	(0x10000)
+/* 2MB granularity */
+#define MMU_SECTION_SHIFT	21
 
 #ifndef __ASSEMBLY__
 
+enum dcache_option {
+	DCACHE_OFF = 0x3,
+};
+
 #define isb()				\
 	({asm volatile(			\
 	"isb" : : : "memory");		\
@@ -265,16 +271,6 @@ enum {
 #endif
 
 /**
- * Change the cache settings for a region.
- *
- * \param start		start address of memory region to change
- * \param size		size of memory region to change
- * \param option	dcache option to select
- */
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option);
-
-/**
  * Register an update to the page tables, and flush the TLB
  *
  * \param start		start address of update in page table
@@ -295,4 +291,17 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 
 #endif /* CONFIG_ARM64 */
 
+#ifndef __ASSEMBLY__
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start		start address of memory region to change
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option);
+
+#endif /* __ASSEMBLY__ */
+
 #endif
-- 
1.7.1