[U-Boot] [PATCH v2 2/7] dm: spi: Correct BIOS protection logic for ICH9
Bin Meng
bmeng.cn at gmail.com
Mon Jun 29 11:06:58 CEST 2015
On Fri, Jun 26, 2015 at 1:55 AM, Simon Glass <sjg at chromium.org> wrote:
> The logic is incorrect and currently has no effect. Fix it so that we can
> write to SPI flash, since by default it is write-protected.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v2:
> - Use ich_read/write() for BIOS protection update
>
> drivers/spi/ich.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index 66a5cba..f68e07b 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -40,6 +40,7 @@ struct ich_spi_priv {
> int status;
> int control;
> int bbar;
> + int bcr;
> uint32_t *pr; /* only for ich9 */
> int speed; /* pointer to speed control */
> ulong max_speed; /* Maximum bus speed in MHz */
> @@ -239,6 +240,7 @@ static int ich_init_controller(struct ich_spi_platdata *plat,
> ctlr->speed = ctlr->control + 2;
> ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
> ctlr->preop = offsetof(struct ich9_spi_regs, preop);
> + ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
> ctlr->pr = &ich9_spi->pr[0];
> ctlr->base = ich9_spi;
> } else {
> @@ -688,13 +690,10 @@ static int ich_spi_probe(struct udevice *bus)
> * v9, deassert SMM BIOS Write Protect Disable.
> */
> if (plat->use_sbase) {
> - struct ich9_spi_regs *ich9_spi;
> -
> - ich9_spi = priv->base;
> - bios_cntl = ich_readb(priv, ich9_spi->bcr);
> + bios_cntl = ich_readb(priv, priv->bcr);
> bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
> bios_cntl |= 1; /* Write Protect Disable (WPD) */
> - ich_writeb(priv, bios_cntl, ich9_spi->bcr);
> + ich_writeb(priv, priv->bcr, bios_cntl);
> } else {
> pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
> if (plat->ich_version == 9)
> --
Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
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