[U-Boot] [PATCH v2] Initial support for ACPI Tables for qemu-x86 target.

[Bin Meng]

Hi Saket,

On Mon, Jun 29, 2015 at 1:08 AM, Saket Sinha <saket.sinha89 at gmail.com> wrote:
> Hi Bin,
>
>>>>> +static unsigned long acpi_fill_mcfg(unsigned long current)
>>>>> +{
>>>>> +       pci_dev_t qemu_dev;
>>>>> +       struct pci_device_id qemu_id[] = { { 0x8086, 0x29c0 } };
>>>>> +        u32 reg;
>>>>> +
>>>>> +        qemu_dev = pci_find_devices(qemu_id, 0);
>>>>> +        if (!qemu_dev)
>>>>> +                return current;
>>>>> +
>>>>> +        reg = pci_read_config_dword(qemu_dev, 0x60, &reg);
>>>>> +        if ((reg & 0x07) != 0x01)  // require enabled + 256MB size
>>>>> +                return current;
>>>>> +
>>>>> +        current += acpi_create_mcfg_mmconfig((struct acpi_mcfg_mmconfig *) current,
>>>>> +                                             reg & 0xf0000000, 0x0, 0x0, 255);
>>>>
>>>> We need actually programming the chipset to enable the ECAM. This
>>>> needs to be done in the arch/x86/cpu/qemu/qemu.c.
>>>>
>>>
>>> Would be needing your guidance for this. Would need some info about
>>> qemu working and  ECAM's role.
>>
>> ECAM is PCIe enhanced configuration access mechanism. QEMU i440FX is a
>> PCI chipset, which does not support ECAM. For QEMU Q35 which supports
>> PCIe, you need check the Q35 chipset. I just checked that, it's on
>> D0:F0:R60h a register called PCIEXBAR. You need hook U-Boot's PCI
>> configuration RW routines to actually use ECAM to verify it is really
>> working.
>>
>
> As suggested by you, I have added below patch -
>
> diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
> index 1a9140b..ba8f470 100644
> --- a/arch/x86/cpu/qemu/pci.c
> +++ b/arch/x86/cpu/qemu/pci.c
> @@ -11,6 +11,8 @@
>  #include <asm/arch/device.h>
>  #include <asm/arch/qemu.h>
>
> +#define Q35_PCIEXBAR_ADDR   0xb0000000
> +
>  DECLARE_GLOBAL_DATA_PTR;
>
>  void board_pci_setup_hose(struct pci_controller *hose)
> @@ -83,7 +85,10 @@ int board_pci_post_scan(struct pci_controller *hose)
>                 x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
>                 x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
>         }
> -
> +       else {
> +               /* setup mmconfig */
> +               x86_pci_write_config32(device, 0x60, Q35_PCIEXBAR_ADDR | 1);
> +       }
>         /*
>          * QEMU emulated graphic card shows in the PCI configuration space with
>          * PCI vendor id and device id as an artificial pair 0x1234:0x1111.
>
> In the bootup logs, with this patch applied, I am getting -
>
> [    0.432000] ACPI: Using PIC for interrupt routing
> [    0.436000] PCI: Using host bridge windows from ACPI; if necessary,
> use "pci=nocrs" and report a bug
> [    0.486000] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
> [    0.488000] acpi PNP0A08:00: _OSC: OS supports [ASPM ClockPM Segments MSI]
> [    0.491000] acpi PNP0A08:00: _OSC: not requesting OS control; OS
> requires [ExtendedConfig ASPM ClockPM MSI]
> [    0.494000] acpi PNP0A08:00: fail to add MMCONFIG information,
> can't access extended PCI configuration space under this bridge.
> [    0.496000] PCI host bridge to bus 0000:00
> [    0.497000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.498000] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
> [    0.498000] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
> [    0.500000] pci_bus 0000:00: root bus resource [mem
> 0x000a0000-0x000bffff window]
> [    0.501000] pci_bus 0000:00: root bus resource [mem
> 0xe0000000-0xfebfffff window]
>
>
> In the log "fail to add MMCONFIG information, can't access extended
> PCI configuration space under this bridge." shows I am still not able
> to use ECAM.
>

I will look into this as well as the cpu uclass sometime this week.

Regards,
Bin