[U-Boot] [PATCH v2 1/7] dm: spi: Correct status register access width

[Jagan Teki]

On 29 June 2015 at 14:33, Bin Meng <bmeng.cn at gmail.com> wrote:
> On Fri, Jun 26, 2015 at 1:55 AM, Simon Glass <sjg at chromium.org> wrote:
>> The status register on ICH9 is a single byte, so use byte access when
>> writing to it, to avoid updating the control register also.
>>
>> Signed-off-by: Simon Glass <sjg at chromium.org>
>> ---
>>
>> Changes in v2:
>> - Continue to use writew for ICH7
>>
>>  drivers/spi/ich.c | 6 +++++-
>>  1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
>> index 6b6cfbf..66a5cba 100644
>> --- a/drivers/spi/ich.c
>> +++ b/drivers/spi/ich.c
>> @@ -411,6 +411,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
>>                         const void *dout, void *din, unsigned long flags)
>>  {
>>         struct udevice *bus = dev_get_parent(dev);
>> +       struct ich_spi_platdata *plat = dev_get_platdata(bus);
>>         struct ich_spi_priv *ctlr = dev_get_priv(bus);
>>         uint16_t control;
>>         int16_t opcode_index;
>> @@ -477,7 +478,10 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
>>         if (ret < 0)
>>                 return ret;
>>
>> -       ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
>> +       if (plat->ich_version == 7)
>> +               ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
>> +       else
>> +               ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
>>
>>         spi_setup_type(trans, using_cmd ? bytes : 0);
>>         opcode_index = spi_setup_opcode(ctlr, trans);
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

Reviewed-by: Jagan Teki <jteki at openedev.com>

thanks!
-- 
Jagan | openedev.