[U-Boot] Marvell Armada XP SATA support

[Anton Schubert]

2015-06-23 14:38 GMT+02:00 Stefan Roese <sr at denx.de>:

> Hi Anton,
>
> On 23.06.2015 13:23, Bin Meng wrote:
>
>> On Tue, Jun 23, 2015 at 5:35 PM, Anton Schubert <anton.schubert at gmx.de>
>> wrote
>>
>
>>> but noticed that there doesn't seem to be a driver for the SATA
>>> controller.
>>> Are there any plans to support SATA on Armada XP or is our only option to
>>> migrate the old driver?
>>>
>>>
>> Is the Marvell SATA controller AHCI compatible? If yes, U-Boot has the
>> AHCI driver which should work.
>>
>
> No, the AXP SATA controller is unfortunately not AHCI compatible (the A38x
> seems to be though). The mvsata driver (drivers/block/mvsata_ide.c) might
> be a pretty good start for the AXP though (I didn't check this closely).
>

Hi,
many thanks for your hints.

I managed to get ide_ident working with mvsata_ide.c by setting the Sata
address windows (using mbus.c analogous to the mvneta driver). But I'm kind
of stuck now as ATA reads will just result in timeouts:

ide_read dev 0 start 0, blocks 1 buffer at 7FBA9C60
ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
ide_outb (dev= 0, port= 0x11c, val= 0xe5) : @ 0xf10a211c
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
ide_inb (dev= 0, port= 0x108) : @ 0xf10a2108 -> 0xff
Powersaving FF
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
ide_outb (dev= 0, port= 0x108, val= 0x01) : @ 0xf10a2108
ide_outb (dev= 0, port= 0x10c, val= 0x00) : @ 0xf10a210c
ide_outb (dev= 0, port= 0x110, val= 0x00) : @ 0xf10a2110
ide_outb (dev= 0, port= 0x114, val= 0x00) : @ 0xf10a2114
ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
ide_outb (dev= 0, port= 0x11c, val= 0x20) : @ 0xf10a211c
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0xd0
ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x51
Error (no IRQ) dev 0 blk 0: status 0x51


This is my current ide config:
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE

/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO

#define CONFIG_SYS_ATA_REG_OFFSET        0x0100      /* Offset for normal
register accesses*/
#define CONFIG_SYS_ATA_DATA_OFFSET    0x0100      /* Offset for data I/O */
#define CONFIG_SYS_ATA_ALT_OFFSET        0x0100      /* Offset for data I/O
*/

/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE        4

/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS          2
#define CONFIG_SYS_IDE_MAXDEVICE       2

/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR    MVEBU_SATA_BASE /* 0xA0000 */
#define CONFIG_SYS_ATA_IDE0_OFFSET    0x2000

#define CONFIG_DOS_PARTITION

I would be grateful for any pointers.

Regards,
Anton