[U-Boot] [PATCH v6 6/6] ti: armv7: am33xx: Move SPL SDRAM into the correct place

Simon Glass sjg at chromium.org
Tue Mar 3 16:03:02 CET 2015


Currently SDRAM is set up before global_data is available. This will soon
not work. Adjust the ordering to cope, using the new CONFIG_SPL_STACK_R
option to ensure that the stack is still in SDRAM once baord_init_r()
starts in SPL.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v6:
- Add new patch for TI boards to avoid gdata

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv7/am33xx/board.c | 13 +++++++++----
 include/configs/ti_armv7_common.h |  3 ++-
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 81477aa..67bef23 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -275,6 +275,14 @@ static void watchdog_disable(void)
 		;
 }
 
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	board_early_init_f();
+	sdram_init();
+}
+#endif
+
 void s_init(void)
 {
 	/*
@@ -290,6 +298,7 @@ void s_init(void)
 	setup_clocks_for_console();
 	uart_soft_reset();
 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
+	/* TODO: This does not work, gd is not available yet */
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
@@ -298,9 +307,5 @@ void s_init(void)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 #endif
-#ifdef CONFIG_SPL_BUILD
-	board_early_init_f();
-	sdram_init();
-#endif
 }
 #endif
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 2bd1164..9e7d94a 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -216,7 +216,8 @@
  * end of the BSS area.  We place our stack at 32MiB after the start of
  * DRAM to allow room for all of the above.
  */
-#define CONFIG_SPL_STACK		(CONFIG_SYS_SDRAM_BASE + (32 << 20))
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_STACK_R		(CONFIG_SYS_SDRAM_BASE + (32 << 20))
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0x80800000
 #endif
-- 
2.2.0.rc0.207.ga3a616c



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