[U-Boot] [PATCH 2/2] spi: Add Cadence QSPI controller Kconfig entry

[Stefan Roese]

On 05.03.2015 17:39, Tom Rini wrote:
> On Thu, Mar 05, 2015 at 05:30:26PM +0100, Stefan Roese wrote:
>> On 05.03.2015 17:14, Marek Vasut wrote:
>>>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>>>> index c0b2570..eaf31ed 100644
>>>>> --- a/drivers/spi/Kconfig
>>>>> +++ b/drivers/spi/Kconfig
>>>>> @@ -16,3 +16,9 @@ config DESIGNWARE_SPI
>>>>>
>>>>>          depends on DM_SPI
>>>>>          help
>>>>>
>>>>>            Enable the Designware SPI driver.
>>>>>
>>>>> +
>>>>> +config CADENCE_QSPI
>>>>> +       bool "Cadence QSPI driver"
>>>>> +       depends on DM_SPI
>>>>> +       help
>>>>> +         Enable the Cadence QSPI driver.
>>>>
>>>> Can we get a bit more detail here? What does QSPI mean? What features
>>>> does it support?
>>>
>>> Stefan ? ;-)
>>
>> Its the IP core from Cadence supporting SPI NOR flash and is present
>> on the Altera SoCFPGA. Enabling access to such SPI NOR flash
>> devices. QSPI stands for Quad-SPI and refers to the optional use of
>> up to 4 data lines for flash access.
>>
>> So perhaps something like this:
>>
>> +
>> +config CADENCE_QSPI
>> +	bool "Cadence QSPI driver"
>> +	depends on DM_SPI
>> +	help
>> +	  Enable the Cadence QSPI driver. This driver can be used to +	
>> access the SPI NOR flash on platforms embedding this
>> +	  Cadence IP core (like the Altera SoCFPGA). QSPI stands for
>> +	  Quad-SPI and refers to the optional use of up to 4 data lines
>> +	  for flash access.
>
> Please don't mention platforms in the help for what I think of as
> IP-block-vendor drivers.  The Cadence QSPI block will be reused by
> others and I can see someone "needing" to patch the help text.  How
> about:
> 	  Enable the Cadence Quad-SPI (QSPI) driver. This driver can be used to
> 	  access the SPI NOR flash on platforms embedding this
> 	  Cadence IP core.

Even better.

Thanks,
Stefan