[U-Boot] [PATCH V4 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

[Nishanth Menon]

On 03/05/2015 10:21 AM, Matt Porter wrote:
> On Tue, Mar 03, 2015 at 04:26:17PM -0600, Nishanth Menon wrote:
>> The fourth incarnation of this series to address review comments on V3
>>
>> With all the usual disclaimers and request to see V1 of the series for a
>> detailed blurb.. As usual additional testing preferred.. Sorry, I dont have
>> access to all possible variants atm..
>>
>> changes since v3:
>> 	- few corrections - i have tried to do a push-pop of register params.
>> 	  hopefully, they should do the job
>> 	- smc with a makefile handling of secure-ext enablement.. (stolen from kernel).
>>
>> V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
>> V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
>> V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
>>
>> Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)
>>
>> BeagleBoard-X15: http://pastebin.ubuntu.com/10518934/
>> 	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
>> 	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040
>>
>> OMAP5uEVM: http://pastebin.ubuntu.com/10518958/
>> 	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
>> 	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040
>>
>> Beagle-XM: http://pastebin.ubuntu.com/10519417/ (this is a r2p3 device)
>> 	Before: CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042
>> 	After: CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042
> 
> I also got the same results on a Beagle-XM Rev. C1
>  
>> I dont have access to other omap3 platforms to give a better coverage
> 
> Beagle Rev. C2 (OMAP3530): http://pastebin.com/f5JcvRf4 
> 	Before: CPUID=0x411fc083 ACR=0x000000e2 L2AUXCR=0x00000042
> 	After: CPUID=0x411fc083 ACR=0x00000042 L2AUXCR=0x00000042
> 
> Tested-by: Matt Porter <mporter at konsulko.com>

Thanks for testing.

> [With build workaround I noted elsewhere in the thread]
> 
that should have been a r1p3 device(needs errata), right and mine
should really be a r3p2?

Did i get the code wrong here? Need some additional eyes here :(

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/Bhccjgga.html

mrc p15, 0, r1, c0, c0, 0       @ r1 has Read Main ID Register (MIDR)
mov r3, r1, lsr #20             @ get variant field
and r3, r3, #0xf                @ r3 has CPU variant
and r4, r1, #0xf                @ r4 has CPU revision

mov r2, r3, lsl #4              @ shift variant field for combined value
orr r2, r4, r2                  @ r2 has combined CPU variant + revision

         cmp     r2, #0x21               @ Only on < r2p1
         bge     skip_errata_621766


-- 
Regards,
Nishanth Menon