[U-Boot] [PATCH V5 05/11] ARM: OMAP: Change set_pl310_ctrl_reg to be generic

[Nishanth Menon]

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup
PL310 control register, however, that is something that is generic
enough to be used for OMAP5 generation of processors as well. The only
difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as
that used in Linux for some consistency). While at that, also add a
data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to
various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by: Nishanth Menon <nm at ti.com>
---
change since V4:
	- back to handcoding smc #0
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   18 +++++++++++-------
 arch/arm/cpu/armv7/omap4/hwinit.c              |    4 ++--
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    5 ++++-
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index e19c7aececdd..80619b04df5d 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -22,11 +22,15 @@ ENTRY(save_boot_params)
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+	PUSH	{r4-r12, lr}	@ save registers - ROM code may pollute
 				@ our registers
-	LDR	r12, =0x102	@ Set PL310 control register - value in R0
-	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
-				@ call ROM Code API to set control register
-	POP	{r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+	MOV	r12, r0		@ Service
+	MOV	r0, r1		@ Argument
+	DSB
+	DMB
+	.word	0xe1600070	@ SMC #0 - hand assembled for GCC versions
+				@ call ROM Code API for the service requested
+
+	POP	{r4-r12, pc}
+ENDPROC(omap_smc1)
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index db16548fac49..9792761d40a0 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -159,11 +159,11 @@ void init_omap_revision(void)
 #ifndef CONFIG_SYS_L2CACHE_OFF
 void v7_outer_cache_enable(void)
 {
-	set_pl310_ctrl_reg(1);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 }
 
 void v7_outer_cache_disable(void)
 {
-	set_pl310_ctrl_reg(0);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index e19975efaf50..f425e3af54f5 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
@@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET	0x102
+
 #endif
-- 
1.7.9.5