[U-Boot] [PATCH V6 08/11] ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

[Tom Rini]

On Mon, Mar 09, 2015 at 05:12:06PM -0500, Nishanth Menon wrote:

> From: Praveen Rao <prao at ti.com>
> 
> This patch enables the workaround for ARM errata 798870 for OMAP5 /
> DRA7 which says "If back-to-back speculative cache line fills (fill
> A and fill B) are issued from the L1 data cache of a CPU to the
> L2 cache, the second request (fill B) is then cancelled, and the
> second request would have detected a hazard against a recent write or
> eviction (write B) to the same cache line as fill B then the L2 logic
> might deadlock."
> 
> An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
> here as well.
> 
> Signed-off-by: Praveen Rao <prao at ti.com>
> Signed-off-by: Angela Stegmaier <angelabaker at ti.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>

Reviewed-by: Tom Rini <trini at konsulko.com>

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20150311/fc1ca37b/attachment.sig>