[U-Boot] [PATCH 1/4] ARM: atmel: arm926ejs: fix clock configuration
Heiko Schocher
hs at denx.de
Tue Mar 17 08:45:16 CET 2015
Hello Bo,
Am 13.03.2015 10:19, schrieb Bo Shen:
> Config MCKR according to the datasheet sequence, or else it
> will cause the MCKR configuration failed.
>
> Remove timeout checking for clock configuration, if configure
> the clock failed, let the system hang while not run in wrong
> clock configuration.
>
> Signed-off-by: Bo Shen <voice.shen at atmel.com>
> ---
>
> arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++++++++++++-----------------
> 1 file changed, 28 insertions(+), 26 deletions(-)
Tested on the corvus and taurus board.
Tested-by: Heiko Schocher <hs at denx.de>
> diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c
> index f363982..8d6934e 100644
> --- a/arch/arm/mach-at91/arm926ejs/clock.c
> +++ b/arch/arm/mach-at91/arm926ejs/clock.c
> @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock)
> void at91_plla_init(u32 pllar)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>
> writel(pllar, &pmc->pllar);
> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
> + ;
just hanging is maybe also bad ... could we hang with adding a
if (timeout == 0) {
debug("could not set PLL(A|B)\n");
timeout = AT91_PLL_LOCK_TIMEOUT;
}
Thinking about it ... have we setup here the debug uart already?
If not, forget my comment
bye,
Heiko
> }
> void at91_pllb_init(u32 pllbr)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
>
> writel(pllbr, &pmc->pllbr);
> - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
> + ;
> }
>
> void at91_mck_init(u32 mckr)
> {
> struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> - int timeout = AT91_PLL_LOCK_TIMEOUT;
> u32 tmp;
>
> tmp = readl(&pmc->mckr);
> - tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
> - AT91_PMC_MCKR_MDIV_MASK |
> - AT91_PMC_MCKR_PLLADIV_MASK |
> - AT91_PMC_MCKR_CSS_MASK);
> - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
> - AT91_PMC_MCKR_MDIV_MASK |
> - AT91_PMC_MCKR_PLLADIV_MASK |
> - AT91_PMC_MCKR_CSS_MASK);
> + tmp &= ~AT91_PMC_MCKR_PRES_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
> writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
>
> - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
> - timeout--;
> - if (timeout == 0)
> - break;
> - }
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> +
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> +
> + tmp = readl(&pmc->mckr);
> + tmp &= ~AT91_PMC_MCKR_CSS_MASK;
> + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
> + writel(tmp, &pmc->mckr);
> + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
> + ;
> }
>
> void at91_periph_clk_enable(int id)
>
--
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