[U-Boot] [PATCH 5/6] armv8/gic: Fix GIC v2 initialization

[Marc Zyngier]

Hi Thierry,

On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding <treding at nvidia.com>
> 
> Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
> interrupts to the primary CPU. This fixes issues seen after booting a
> Linux kernel from U-Boot.
> 
> Suggested-by: Marc Zyngier <marc.zyngier at arm.com>
> Suggested-by: Mark Rutland <mark.rutland at arm.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Thierry Reding <treding at nvidia.com>
> ---
>  arch/arm/lib/gic_64.S | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
> index a3e18f7713e5..62d0022408bc 100644
> --- a/arch/arm/lib/gic_64.S
> +++ b/arch/arm/lib/gic_64.S
> @@ -46,11 +46,19 @@ ENTRY(gic_init_secure)
>  	ldr	w9, [x0, GICD_TYPER]
>  	and	w10, w9, #0x1f		/* ITLinesNumber */
>  	cbz	w10, 1f			/* No SPIs */
> -	add	x11, x0, (GICD_IGROUPRn + 4)
> +	add	x11, x0, GICD_IGROUPRn
>  	mov	w9, #~0			/* Config SPIs as Grp1 */
> +	str	w9, [x11], #0x4
>  0:	str	w9, [x11], #0x4
>  	sub	w10, w10, #0x1
>  	cbnz	w10, 0b
> +
> +	ldr	x1, =GICC_BASE		/* GICC_CTLR */
> +	mov	w0, #3			/* EnableGrp0 | EnableGrp1 */
> +	str	w0, [x1]
> +
> +	mov	w0, #1 << 7		/* allow NS access to GICC_PMR */
> +	str	w0, [x1, #4]		/* GICC_PMR */
>  #endif
>  1:
>  	ret
> 

Looking at the code that currently sits in the u-boot repo, it looks
like you are duplicating functionality that is provided by
gic_init_secure_percpu.

Could your boot failure be a case of this function not being called on
all CPUs?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...