[U-Boot] [PATCH v5 06/28] armv8/fsl-lsch3: Set nodes in DVM domain
York Sun
yorksun at freescale.com
Sat Mar 21 03:28:10 CET 2015
From: Scott Wood <scottwood at freescale.com>
This is required for TLB invalidation broadcasts to work.
Signed-off-by: Scott Wood <scottwood at freescale.com>
Signed-off-by: York Sun <yorksun at freescale.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 9 +++++++++
arch/arm/include/asm/arch-fsl-lsch3/config.h | 6 ++++++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 53bdb44..018c617 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -15,6 +15,15 @@
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
+ /* Add fully-coherent masters to DVM domain */
+ ldr x1, =CCI_MN_BASE
+ ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST]
+ str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+ mvn x0, x3
+ tst x0, x3 /* Wait for domain addition to complete */
+ b.ne 1b
+
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 518e59c..9121452 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -118,6 +118,12 @@
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE 0x04000000
+#define CCI_MN_RNF_NODEID_LIST 0x180
+#define CCI_MN_DVM_DOMAIN_CTL 0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
--
1.7.9.5
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