[U-Boot] [PATCH 2/3] sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig
Paul Kocialkowski
contact at paulk.fr
Sun Mar 22 18:12:23 CET 2015
Sunxi platforms have different possible mmc pin mux setups (except for mmc0),
which are different across platforms.
This lets users configure which is used through the CONFIG_MMC*_PINS Kconfig
options. This is especially relevant when a second (in addition to mmc0) port
is used and CONFIG_MMC_SUNXI_SLOT_EXTRA is enabled.
Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
arch/arm/include/asm/arch-sunxi/gpio.h | 13 +++-
board/sunxi/Kconfig | 19 +++++
board/sunxi/board.c | 131 +++++++++++++++++++++++++++++++--
drivers/gpio/sunxi_gpio.c | 14 ++++
4 files changed, 171 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index a6b15d6..f227044 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -145,26 +145,36 @@ enum sunxi_gpio_number {
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
+#define SUN6I_GPA_SDC2 5
+#define SUN6I_GPA_SDC3 4
#define SUNXI_GPB_TWI0 2
#define SUN4I_GPB_UART0 2
#define SUN5I_GPB_UART0 2
#define SUNXI_GPC_SDC2 3
+#define SUN6I_GPC_SDC3 4
+#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
+#define SUN5I_GPE_SDC2 3
+
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART0 4
#define SUN8I_GPF_UART0 3
+#define SUN4I_GPG_SDC1 4
#define SUN5I_GPG_SDC1 2
+#define SUN6I_GPG_SDC1 2
+#define SUN8I_GPG_SDC1 2
#define SUN5I_GPG_UART1 4
+#define SUN4I_GPH_SDC1 5
#define SUN6I_GPH_UART0 2
-#define SUN4I_GPI_SDC3 2
+#define SUNXI_GPI_SDC3 2
#define SUN6I_GPL0_R_P2WI_SCK 3
#define SUN6I_GPL1_R_P2WI_SDA 3
@@ -189,6 +199,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
int sunxi_name_to_gpio(const char *name);
#define name_to_gpio(name) sunxi_name_to_gpio(name)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5639321..57e7529 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -208,6 +208,25 @@ config MMC3_CD_PIN
---help---
See MMC0_CD_PIN help text.
+config MMC1_PINS
+ string "Pins for mmc1"
+ default ""
+ ---help---
+ Set the pins used for mmc1, when applicable. This takes a string in the
+ format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
+
+config MMC2_PINS
+ string "Pins for mmc2"
+ default ""
+ ---help---
+ See MMC1_PINS help text.
+
+config MMC3_PINS
+ string "Pins for mmc3"
+ default ""
+ ---help---
+ See MMC1_PINS help text.
+
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
default -1
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3af3973..01b654e 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -71,10 +71,11 @@ int dram_init(void)
static void mmc_pinmux_setup(int sdc)
{
unsigned int pin;
+ int pins;
switch (sdc) {
case 0:
- /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+ /* SDC0: PF0-PF5 */
for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
@@ -83,30 +84,150 @@ static void mmc_pinmux_setup(int sdc)
break;
case 1:
- /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ if (pins == SUNXI_GPIO_H) {
+ /* SDC1: PH22-PH-27 */
+ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#elif defined(CONFIG_MACH_SUN5I)
+ /* SDC1: PG3-PG8 */
for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN6I)
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#elif defined(CONFIG_MACH_SUN8I)
+ if (pins == SUNXI_GPIO_D) {
+ /* SDC1: PD2-PD7 */
+ for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC1: PG0-PG5 */
+ for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#endif
break;
case 2:
- /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* SDC2: PC6-PC11 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN5I)
+ if (pins == SUNXI_GPIO_E) {
+ /* SDC2: PE4-PE9 */
+ for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC2: PC6-PC15 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#elif defined(CONFIG_MACH_SUN6I)
+ if (pins == SUNXI_GPIO_A) {
+ /* SDC2: PA9-PA14 */
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC2: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ }
+#elif defined(CONFIG_MACH_SUN8I)
+ /* SDC2: PC5-PC6, PC8-PC16 */
+ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#endif
break;
case 3:
- /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+ /* SDC3: PI4-PI9 */
for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
- sunxi_gpio_set_cfgpin(pin, SUN4I_GPI_SDC3);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN6I)
+ if (pins == SUNXI_GPIO_A) {
+ /* SDC3: PA9-PA14 */
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC3: PC6-PC15, PC24 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
+ }
+#endif
break;
default:
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index c66aa51..532d489 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -115,6 +115,20 @@ int gpio_set_value(unsigned gpio, int value)
return sunxi_gpio_output(gpio, value);
}
+int sunxi_name_to_gpio_bank(const char *name)
+{
+ int group = 0;
+
+ if (*name == 'P' || *name == 'p')
+ name++;
+ if (*name >= 'A') {
+ group = *name - (*name > 'a' ? 'a' : 'A');
+ return group;
+ }
+
+ return -1;
+}
+
int sunxi_name_to_gpio(const char *name)
{
int group = 0;
--
1.9.1
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