[U-Boot] [PATCH v5 26/28] armv8/ls2085ardb: Enable NAND SPL support

[Scott Wood]

On Fri, 2015-03-20 at 19:28 -0700, York Sun wrote:
> diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
> index cfd5185..5a5171c 100644
> --- a/board/freescale/ls2085ardb/README
> +++ b/board/freescale/ls2085ardb/README
> @@ -107,3 +107,22 @@ Booting Options
>  ---------------
>  a) NOR boot
>  b) NAND boot
> +
> +Generage NAND image

Generate

> +-------------------
> +To form the NAND image, build u-boot with LS2085ARDB_NAND_defconfig.
> +Append u-boot-with-spl.bin after RCW image.

I thought we were going to put the SPL image in a separate erase block,
rather than concatenate it to the PBI.

>  The RCW image should
> +have these PBI commands
> +
> +1) CCSR 4-byte write to 0x00e00404, data=0x00000000
> +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
> +3) Block Copy: SRC=0x0104, SRC_ADDR=0x000000c0, DEST_ADDR=0x1800a000,
> +BLOCK_SIZE=0x00014000

0xc0 assumes that's the size of the PBI.  This is one reason I don't
like the concatenated approach.

> +These PBI commands set the bootloc registers to OCRAM address 0x1800a000
> +and the SPL image is copied from the combined image into OCRAM.
> +
> +The SRC_ADDR should match the size of RCW image, i.e. it is the offset
> +of u-boot-with-spl.bin in the NAND image. If putting RCW in a separated
> +block is desired, the offset needs adjustment. Padding between the end
> +of RCW and the start of u-boot image may be required.

The padding between SPL and main U-Boot and other constants would also
need to change.  I don't think we want to make this a user knob.

-Scott