[U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming

[FengHua]

> -----Original Messages-----
> From: "Thierry Reding" <thierry.reding at gmail.com>
> Sent Time: 2015-03-20 19:47:50 (Friday)
> To: u-boot at lists.denx.de
> Cc: "Marc Zyngier" <marc.zyngier at arm.com>
> Subject: [U-Boot] [PATCH 3/6] armv8/mmu: Clean up TCR programming
> 
> From: Thierry Reding <treding at nvidia.com>
> 
> Use the inner shareable attribute for memory, which makes more sense
> considering that this code is called when caches are being enabled.
> 
> While at it, fix the values for the shareability attribute field to
> match the documentation.
> 
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Signed-off-by: Thierry Reding <treding at nvidia.com>
> ---
>  arch/arm/include/asm/armv8/mmu.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
> index 4b9cb5296572..6d42f5533a74 100644
> --- a/arch/arm/include/asm/armv8/mmu.h
> +++ b/arch/arm/include/asm/armv8/mmu.h
> @@ -93,8 +93,8 @@
>  #define TCR_ORGN_WBNWA		(3 << 10)
>  #define TCR_ORGN_MASK		(3 << 10)
>  #define TCR_SHARED_NON		(0 << 12)
> -#define TCR_SHARED_OUTER	(1 << 12)
> -#define TCR_SHARED_INNER	(2 << 12)
> +#define TCR_SHARED_OUTER	(2 << 12)
> +#define TCR_SHARED_INNER	(3 << 12)
>  #define TCR_TG0_4K		(0 << 14)
>  #define TCR_TG0_64K		(1 << 14)
>  #define TCR_TG0_16K		(2 << 14)
> @@ -102,9 +102,9 @@
>  #define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
>  #define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
>  
> -/* PTWs cacheable, inner/outer WBWA and non-shareable */
> +/* PTWs cacheable, inner/outer WBWA and inner shareable */
>  #define TCR_FLAGS		(TCR_TG0_64K |		\
> -				TCR_SHARED_NON |	\
> +				TCR_SHARED_INNER |	\
>  				TCR_ORGN_WBWA |		\
>  				TCR_IRGN_WBWA |		\
>  				TCR_T0SZ(VA_BITS))
> -- 
> 2.3.2

Acked-by: david.feng <fenghua at phytium.com.cn>