[U-Boot] [PATCH] drivers:usb:fsl: Implement Erratum A-009116 for XHCI controller

[Nikhil Badola]

This adjusts (micro)frame length to appropriate value thus
avoiding USB devices to time out over a longer run

Signed-off-by: Nikhil Badola <nikhil.badola at freescale.com>
---
Depends on fsl/usb: Add USB XHCI support
http://patchwork.ozlabs.org/patch/373593/

 drivers/usb/host/xhci-fsl.c  |  9 +++++++++
 include/linux/usb/dwc3.h     | 19 +++++++++++++------
 include/linux/usb/xhci-fsl.h |  2 ++
 3 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 1d25084..981cf17 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -29,6 +29,12 @@ inline int __board_usb_init(int index, enum usb_init_type init)
 int board_usb_init(int index, enum usb_init_type init)
 	__attribute__((weak, alias("__board_usb_init")));
 
+static void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
+{
+	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
+		     GFLADJ_30MHZ(val));
+}
+
 static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
 {
 	clrsetbits_le32(&dwc3_reg->g_ctl,
@@ -100,6 +106,9 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 	/* We are hard-coding DWC3 core to Host Mode */
 	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
 
+	/* Set GFLADJ_30MHZ value as per Erratum A009116 */
+	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
 	return ret;
 }
 
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 7edc760..13d58e9 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -109,7 +109,11 @@ struct dwc3 {					/* offset: 0xC100 */
 
 	u32 g_hwparams8;
 
-	u32 reserved4[63];
+	u32 reserved4[11];
+
+	u32 g_fladj;
+
+	u32 reserved5[51];
 
 	u32 d_cfg;
 	u32 d_ctl;
@@ -118,15 +122,15 @@ struct dwc3 {					/* offset: 0xC100 */
 	u32 d_gcmdpar;
 	u32 d_gcmd;
 
-	u32 reserved5[2];
+	u32 reserved6[2];
 
 	u32 d_alepena;
 
-	u32 reserved6[55];
+	u32 reserved7[55];
 
 	struct d_physical_endpoint d_phy_ep_cmd[32];
 
-	u32 reserved7[128];
+	u32 reserved8[128];
 
 	u32 o_cfg;
 	u32 o_ctl;
@@ -134,7 +138,7 @@ struct dwc3 {					/* offset: 0xC100 */
 	u32 o_evten;
 	u32 o_sts;
 
-	u32 reserved8[3];
+	u32 reserved9[3];
 
 	u32 adp_cfg;
 	u32 adp_ctl;
@@ -143,7 +147,7 @@ struct dwc3 {					/* offset: 0xC100 */
 
 	u32 bc_cfg;
 
-	u32 reserved9;
+	u32 reserved10;
 
 	u32 bc_evt;
 	u32 bc_evten;
@@ -191,4 +195,7 @@ struct dwc3 {					/* offset: 0xC100 */
 #define DWC3_DCTL_CSFTRST			(1 << 30)
 #define DWC3_DCTL_LSFTRST			(1 << 29)
 
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL			(1 << 7)
+#define GFLADJ_30MHZ(n)				((n) & 0x3f)
 #endif /* __DWC3_H_ */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index 54b7e8b..22a65e9 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -10,6 +10,8 @@
 #ifndef _ASM_ARCH_XHCI_FSL_H_
 #define _ASM_ARCH_XHCI_FSL_H_
 
+#define GFLADJ_30MHZ_DEFAULT	0x20
+
 /* USBOTGSS_WRAPPER definitions */
 #define USBOTGSS_WRAPRESET	(1 << 17)
 #define USBOTGSS_DMADISABLE (1 << 16)
-- 
1.7.11.7