[U-Boot] [PATCH] mpc85xx/T1040D4RDB: Disable all CPLD interrupts, except QSGMI1 and QSGMI2

[Codrin Ciubotariu]

By default, CPLD used by Freescale's T1040D4RDB has all the interrupt
sources enabled. If the interrupt line is enabled in the OS and one of
these sources rises the interrupt without having a driver to handle it,
then the board will get an interrupt storm.

This patch masks all the interrupts available in CPLD with exception
for QSGMII PHY interrupts, for which we have a driver in Linux.

This patch depends on patches:
mpc85xx/T104xD4RDB: Add T104xD4RDB boards support
mpc85xx/T1042D4RDB: Select DIU in cpld mux for T1042D4RDB

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu at freescale.com>
---
 board/freescale/t104xrdb/cpld.c     |  2 +-
 board/freescale/t104xrdb/cpld.h     |  2 +-
 board/freescale/t104xrdb/t104xrdb.c | 11 +++++++++++
 include/configs/T104xRDB.h          |  6 ++++++
 4 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index df0e348..12b4126 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -69,7 +69,7 @@ static void cpld_dump_regs(void)
 	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
 	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
 	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
-	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+	printf("int_mask	 = 0x%02x\n", CPLD_READ(int_mask));
 	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
 	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
 	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index 543ab53..d4cfc87 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -21,7 +21,7 @@ struct cpld_data {
 	u8 int_status;		/* 0x12 - Interrupt status Register */
 	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
 	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
-	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+	u8 int_mask;		/* 0x15 - Interrupt mask Register */
 	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
 	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
 	u8 boot_override;	/* 0x18 - Boot override register */
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 963cae4..c4b658d 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -112,6 +112,17 @@ int misc_init_r(void)
 		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 
+#if defined(CONFIG_T1040D4RDB)
+	/* Mask all CPLD interrupt sources, except QSGMII interrupts */
+	if (CPLD_READ(sw_ver) < 0x03) {
+		debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+		      CPLD_READ(sw_ver));
+	} else {
+		CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+			   ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+	}
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 91c567d..fd19fb3 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -295,6 +295,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CPLD_DIU_SEL_DFP		0xc0
 #endif
 
+#if defined(CONFIG_T1040D4RDB)
+#define CPLD_INT_MASK_ALL              0xFF
+#define CPLD_INT_MASK_QSGMII1          0x20
+#define CPLD_INT_MASK_QSGMII2          0x10
+#endif
+
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000
 #define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 #define CONFIG_SYS_CSPR2_EXT	(0xf)
-- 
1.9.3