[U-Boot] [PATCH 1/6] sh: Remove rsk7264 board
Joe Hershberger
joe.hershberger at ni.com
Sun May 10 22:23:09 CEST 2015
Removing this board because it does not build with any tool-chain that
we know of.
The board fails to build with the tool-chain available at kernel.org:
https://www.kernel.org/pub/tools/crosstool/files/bin/i686/4.6.3/i686-gcc-4.6.3-nolibc_sh4-linux.tar.xz
It fails with the following errors:
sh4-linux-gcc: error: command line option '-m2a' is not supported by this configuration
sh4-linux-gcc: error: command line option '-m2a-nofpu' is not supported by this configuration
Signed-off-by: Joe Hershberger <joe.hershberger at ni.com>
Cc: Phil Edworthy <phil.edworthy at renesas.com>
---
arch/sh/Kconfig | 5 -
arch/sh/include/asm/cpu_sh2.h | 2 -
arch/sh/include/asm/cpu_sh7264.h | 41 -------
board/renesas/rsk7264/Kconfig | 12 --
board/renesas/rsk7264/MAINTAINERS | 6 -
board/renesas/rsk7264/Makefile | 7 --
board/renesas/rsk7264/lowlevel_init.S | 210 ----------------------------------
board/renesas/rsk7264/rsk7264.c | 71 ------------
configs/rsk7264_defconfig | 2 -
drivers/serial/serial_sh.h | 3 +-
include/configs/rsk7264.h | 74 ------------
11 files changed, 1 insertion(+), 432 deletions(-)
delete mode 100644 arch/sh/include/asm/cpu_sh7264.h
delete mode 100644 board/renesas/rsk7264/Kconfig
delete mode 100644 board/renesas/rsk7264/MAINTAINERS
delete mode 100644 board/renesas/rsk7264/Makefile
delete mode 100644 board/renesas/rsk7264/lowlevel_init.S
delete mode 100644 board/renesas/rsk7264/rsk7264.c
delete mode 100644 configs/rsk7264_defconfig
delete mode 100644 include/configs/rsk7264.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 2128f23..395138e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -34,10 +34,6 @@ config TARGET_RSK7203
bool "RSK+ 7203"
select CPU_SH2A
-config TARGET_RSK7264
- bool "RSK2+SH7264"
- select CPU_SH2A
-
config TARGET_RSK7269
bool "RSK2+SH7269"
select CPU_SH2A
@@ -140,7 +136,6 @@ source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
source "board/renesas/rsk7203/Kconfig"
-source "board/renesas/rsk7264/Kconfig"
source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig"
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
index 18a0f0b..1d0a683 100644
--- a/arch/sh/include/asm/cpu_sh2.h
+++ b/arch/sh/include/asm/cpu_sh2.h
@@ -20,8 +20,6 @@
#if defined(CONFIG_CPU_SH7203)
# include <asm/cpu_sh7203.h>
-#elif defined(CONFIG_CPU_SH7264)
-# include <asm/cpu_sh7264.h>
#elif defined(CONFIG_CPU_SH7269)
# include <asm/cpu_sh7269.h>
#else
diff --git a/arch/sh/include/asm/cpu_sh7264.h b/arch/sh/include/asm/cpu_sh7264.h
deleted file mode 100644
index a4a4d51..0000000
--- a/arch/sh/include/asm/cpu_sh7264.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_CPU_SH7264_H_
-#define _ASM_CPU_SH7264_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-
-/* SDRAM controller */
-
-/* SCIF */
-#define SCSMR_3 0xFFFE9800
-#define SCIF3_BASE SCSMR_3
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-#define CMCSR_1 0xFFFEC008
-#define CMCNT_1 0xFFFEC00A
-#define CMCOR_1 0xFFFEC00C
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7264_H_ */
diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig
deleted file mode 100644
index 755d289..0000000
--- a/board/renesas/rsk7264/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RSK7264
-
-config SYS_BOARD
- default "rsk7264"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7264"
-
-endif
diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS
deleted file mode 100644
index f6202b7..0000000
--- a/board/renesas/rsk7264/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RSK7264 BOARD
-M: Phil Edworthy <phil.edworthy at renesas.com>
-S: Maintained
-F: board/renesas/rsk7264/
-F: include/configs/rsk7264.h
-F: configs/rsk7264_defconfig
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
deleted file mode 100644
index 7ada697..0000000
--- a/board/renesas/rsk7264/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2011 Renesas Electronics Europe Ltd.
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := rsk7264.o
-obj-y += lowlevel_init.o
diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S
deleted file mode 100644
index eae2703..0000000
--- a/board/renesas/rsk7264/lowlevel_init.S
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on board/renesas/rsk7203/lowlevel_init.S
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* io_set_cpg */
- write8 STBCR3_A, STBCR3_D
- write8 STBCR4_A, STBCR4_D
- write8 STBCR5_A, STBCR5_D
- write8 STBCR6_A, STBCR6_D
- write8 STBCR7_A, STBCR7_D
- write8 STBCR8_A, STBCR8_D
-
- /* ConfigurePortPins */
-
- /* Leaving LED1 ON for sanity test */
- write16 PJCR1_A, PJCR1_D1
- write16 PJCR2_A, PJCR2_D
- write16 PJIOR0_A, PJIOR0_D1
- write16 PJDR0_A, PJDR0_D
- write16 PJPR0_A, PJPR0_D
-
- /* Configure EN_PIN & RS_PIN */
- write16 PGCR2_A, PGCR2_D
- write16 PGIOR0_A, PGIOR0_D
-
- /* Configure the port pins connected to UART */
- write16 PJCR1_A, PJCR1_D2
- write16 PJIOR0_A, PJIOR0_D2
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
- write16 WTCSR_A, WTCSR_D1
- write16 WTCNT_A, WTCNT_D
-
- /* Control of RESBANK */
- write16 IBNR_A, IBNR_D
- /* Enable SCIF3 module */
- write16 STBCR4_A, STBCR4_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
-
-pfc_settings:
- write16 PCCR2_A, PCCR2_D
- write16 PCCR1_A, PCCR1_D
- write16 PCCR0_A, PCCR0_D
-
- write16 PBCR0_A, PBCR0_D
- write16 PBCR1_A, PBCR1_D
- write16 PBCR2_A, PBCR2_D
- write16 PBCR3_A, PBCR3_D
- write16 PBCR4_A, PBCR4_D
- write16 PBCR5_A, PBCR5_D
-
- write16 PDCR0_A, PDCR0_D
- write16 PDCR1_A, PDCR1_D
- write16 PDCR2_A, PDCR2_D
- write16 PDCR3_A, PDCR3_D
-
- write32 CS0WCR_A, CS0WCR_D
- write32 CS0BCR_A, CS0BCR_D
-
-init_bsc_cs2:
- write16 PJCR0_A, PJCR0_D
- write32 CS2WCR_A, CS2WCR_D
-
-init_sdram:
- write32 CS3BCR_A, CS3BCR_D
- write32 CS3WCR_A, CS3WCR_D
- write32 SDCR_A, SDCR_D
- write32 RTCOR_A, RTCOR_D
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x1003
-.align 2
-STBCR3_A: .long 0xFFFE0408
-STBCR3_D: .long 0x00000002
-STBCR4_A: .long 0xFFFE040C
-STBCR4_D: .word 0x0000
-.align 2
-STBCR5_A: .long 0xFFFE0410
-STBCR5_D: .long 0x00000010
-STBCR6_A: .long 0xFFFE0414
-STBCR6_D: .long 0x00000002
-STBCR7_A: .long 0xFFFE0418
-STBCR7_D: .long 0x0000002A
-STBCR8_A: .long 0xFFFE041C
-STBCR8_D: .long 0x0000007E
-PJCR1_A: .long 0xFFFE390C
-PJCR1_D1: .word 0x0000
-PJCR1_D2: .word 0x0022
-PJCR2_A: .long 0xFFFE390A
-PJCR2_D: .word 0x0000
-.align 2
-PJIOR0_A: .long 0xFFFE3912
-PJIOR0_D1: .word 0x0FC0
-PJIOR0_D2: .word 0x0FE0
-PJDR0_A: .long 0xFFFE3916
-PJDR0_D: .word 0x0FBF
-.align 2
-PJPR0_A: .long 0xFFFE391A
-PJPR0_D: .long 0x00000FBF
-PGCR2_A: .long 0xFFFE38CA
-PGCR2_D: .word 0x0000
-.align 2
-PGIOR0_A: .long 0xFFFE38D2
-PGIOR0_D: .word 0x03F0
-.align 2
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0x0000
-WTCSR_D1: .word 0x0000
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x0000
-.align 2
-PCCR0_A: .long 0xFFFE384E
-PDCR0_A: .long 0xFFFE386E
-PDCR1_A: .long 0xFFFE386C
-PDCR2_A: .long 0xFFFE386A
-PDCR3_A: .long 0xFFFE3868
-PBCR0_A: .long 0xFFFE382E
-PBCR1_A: .long 0xFFFE382C
-PBCR2_A: .long 0xFFFE382A
-PBCR3_A: .long 0xFFFE3828
-PBCR4_A: .long 0xFFFE3826
-PBCR5_A: .long 0xFFFE3824
-PCCR0_D: .word 0x1111
-PDCR0_D: .word 0x1111
-PDCR1_D: .word 0x1111
-PDCR2_D: .word 0x1111
-PDCR3_D: .word 0x1111
-PBCR0_D: .word 0x1110
-PBCR1_D: .word 0x1111
-PBCR2_D: .word 0x1111
-PBCR3_D: .word 0x1111
-PBCR4_D: .word 0x1111
-PBCR5_D: .word 0x0111
-.align 2
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-PJCR0_A: .long 0xFFFE390E
-PJCR0_D: .word 0x3300
-.align 2
-CS2WCR_A: .long 0xFFFC0030
-CS2WCR_D: .long 0x00000B01
-PCCR2_A: .long 0xFFFE384A
-PCCR2_D: .word 0x0001
-.align 2
-PCCR1_A: .long 0xFFFE384C
-PCCR1_D: .word 0x1111
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x0000288A
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000812
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0046
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xA55A0010
-IBNR_A: .long 0xFFFE080E
-IBNR_D: .word 0x0000
-.align 2
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00000085
diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c
deleted file mode 100644
index d938b3a..0000000
--- a/board/renesas/rsk7264/rsk7264.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on u-boot/board/rsk7264/rsk7203.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7264\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC89218 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig
deleted file mode 100644
index aedc333..0000000
--- a/configs/rsk7264_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SH=y
-CONFIG_TARGET_RSK7264=y
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 941e6ed..8cefa65 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -188,8 +188,7 @@ struct uart_port {
#elif defined(CONFIG_CPU_SH7201) || \
defined(CONFIG_CPU_SH7203) || \
defined(CONFIG_CPU_SH7206) || \
- defined(CONFIG_CPU_SH7263) || \
- defined(CONFIG_CPU_SH7264)
+ defined(CONFIG_CPU_SH7263)
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
deleted file mode 100644
index 2ecf785..0000000
--- a/include/configs/rsk7264.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Configuation settings for the Renesas RSK2+SH7264 board
- *
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __RSK7264_H
-#define __RSK7264_H
-
-#undef DEBUG
-#define CONFIG_CPU_SH7264 1
-#define CONFIG_RSK7264 1
-
-#ifndef _CONFIG_CMD_DEFAULT_H
-# include <config_cmd_default.h>
-#endif
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS "console=ttySC3,115200"
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
-
-/* Serial */
-#define CONFIG_SCIF_CONSOLE 1
-#define CONFIG_CONS_SCIF3 1
-
-/* Memory */
-/* u-boot relocated to top 256KB of ram */
-#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
-#define CONFIG_SYS_SDRAM_BASE 0x0C000000
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-
-/* Flash */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET (128 * 1024)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-/* Network interface */
-#define CONFIG_SMC911X
-#define CONFIG_SMC911X_16_BIT
-#define CONFIG_SMC911X_BASE 0x28000000
-
-#endif /* __RSK7264_H */
--
1.7.11.5
More information about the U-Boot
mailing list