[U-Boot] [PATCH 5/6] sh: Remove ms7720se board
Joe Hershberger
joe.hershberger at ni.com
Sun May 10 22:23:13 CEST 2015
Removing this board because it does not build with any tool-chain that
we know of.
The board fails to build with the tool-chain available at kernel.org:
https://www.kernel.org/pub/tools/crosstool/files/bin/i686/4.6.3/i686-gcc-4.6.3-nolibc_sh4-linux.tar.xz
It fails with the following error:
sh4-linux-gcc: error: command line option '-m3' is not supported by this configuration
Signed-off-by: Joe Hershberger <joe.hershberger at ni.com>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh at renesas.com>
---
arch/sh/Kconfig | 5 -
arch/sh/include/asm/cpu_sh3.h | 2 -
arch/sh/include/asm/cpu_sh7720.h | 207 ---------------------------------------
board/ms7720se/Kconfig | 9 --
board/ms7720se/MAINTAINERS | 6 --
board/ms7720se/Makefile | 16 ---
board/ms7720se/lowlevel_init.S | 185 ----------------------------------
board/ms7720se/ms7720se.c | 46 ---------
configs/ms7720se_defconfig | 2 -
doc/README.sh | 16 +--
drivers/serial/serial_sh.h | 8 +-
include/configs/ms7720se.h | 109 ---------------------
12 files changed, 3 insertions(+), 608 deletions(-)
delete mode 100644 arch/sh/include/asm/cpu_sh7720.h
delete mode 100644 board/ms7720se/Kconfig
delete mode 100644 board/ms7720se/MAINTAINERS
delete mode 100644 board/ms7720se/Makefile
delete mode 100644 board/ms7720se/lowlevel_init.S
delete mode 100644 board/ms7720se/ms7720se.c
delete mode 100644 configs/ms7720se_defconfig
delete mode 100644 include/configs/ms7720se.h
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 119db89..a4a32b2 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -23,10 +23,6 @@ config SH_32BIT
choice
prompt "Target select"
-config TARGET_MS7720SE
- bool "Support ms7720se"
- select CPU_SH3
-
config TARGET_SHMIN
bool "SHMIN"
select CPU_SH3
@@ -105,7 +101,6 @@ config USE_PRIVATE_LIBGCC
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
-source "board/ms7720se/Kconfig"
source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h
index 0c85e94..443aaeb 100644
--- a/arch/sh/include/asm/cpu_sh3.h
+++ b/arch/sh/include/asm/cpu_sh3.h
@@ -22,8 +22,6 @@
#include <asm/cpu_sh7706.h>
#elif defined(CONFIG_CPU_SH7710)
#include <asm/cpu_sh7710.h>
-#elif defined(CONFIG_CPU_SH7720)
-#include <asm/cpu_sh7720.h>
#else
#error "Unknown SH3 variant"
#endif
diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h
deleted file mode 100644
index 6a861bd..0000000
--- a/arch/sh/include/asm/cpu_sh7720.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright 2007 (C)
- * Yoshihiro Shimoda <shimoda.yoshihiro at renesas.com>
- *
- * Copyright 2008 (C)
- * Mark Jonas <mark.jonas at de.bosch.com>
- *
- * SH7720 Internal I/O register
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_CPU_SH7720_H_
-#define _ASM_CPU_SH7720_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000B
-
-/* EXP */
-#define TRA 0xFFFFFFD0
-#define EXPEVT 0xFFFFFFD4
-#define INTEVT 0xFFFFFFD8
-
-/* MMU */
-#define MMUCR 0xFFFFFFE0
-#define PTEH 0xFFFFFFF0
-#define PTEL 0xFFFFFFF4
-#define TTB 0xFFFFFFF8
-
-/* CACHE */
-#define CCR 0xFFFFFFEC
-
-/* INTC */
-#define IPRF 0xA4080000
-#define IPRG 0xA4080002
-#define IPRH 0xA4080004
-#define IPRI 0xA4080006
-#define IPRJ 0xA4080008
-#define IRR5 0xA4080020
-#define IRR6 0xA4080022
-#define IRR7 0xA4080024
-#define IRR8 0xA4080026
-#define IRR9 0xA4080028
-#define IRR0 0xA4140004
-#define IRR1 0xA4140006
-#define IRR2 0xA4140008
-#define IRR3 0xA414000A
-#define IRR4 0xA414000C
-#define ICR1 0xA4140010
-#define ICR2 0xA4140012
-#define PINTER 0xA4140014
-#define IPRC 0xA4140016
-#define IPRD 0xA4140018
-#define IPRE 0xA414001A
-#define ICR0 0xA414FEE0
-#define IPRA 0xA414FEE2
-#define IPRB 0xA414FEE4
-
-/* BSC */
-#define BSC_BASE 0xA4FD0000
-#define CMNCR (BSC_BASE + 0x00)
-#define CS0BCR (BSC_BASE + 0x04)
-#define CS2BCR (BSC_BASE + 0x08)
-#define CS3BCR (BSC_BASE + 0x0C)
-#define CS4BCR (BSC_BASE + 0x10)
-#define CS5ABCR (BSC_BASE + 0x14)
-#define CS5BBCR (BSC_BASE + 0x18)
-#define CS6ABCR (BSC_BASE + 0x1C)
-#define CS6BBCR (BSC_BASE + 0x20)
-#define CS0WCR (BSC_BASE + 0x24)
-#define CS2WCR (BSC_BASE + 0x28)
-#define CS3WCR (BSC_BASE + 0x2C)
-#define CS4WCR (BSC_BASE + 0x30)
-#define CS5AWCR (BSC_BASE + 0x34)
-#define CS5BWCR (BSC_BASE + 0x38)
-#define CS6AWCR (BSC_BASE + 0x3C)
-#define CS6BWCR (BSC_BASE + 0x40)
-#define SDCR (BSC_BASE + 0x44)
-#define RTCSR (BSC_BASE + 0x48)
-#define RTCNR (BSC_BASE + 0x4C)
-#define RTCOR (BSC_BASE + 0x50)
-#define SDMR2 (BSC_BASE + 0x4000)
-#define SDMR3 (BSC_BASE + 0x5000)
-
-/* DMAC */
-
-/* CPG */
-#define UCLKCR 0xA40A0008
-#define FRQCR 0xA415FF80
-
-/* LOW POWER MODE */
-
-/* TMU */
-#define TMU_BASE 0xA412FE90
-
-/* TPU */
-#define TPU_BASE 0xA4480000
-#define TPU_TSTR (TPU_BASE + 0x00)
-#define TPU_TCR0 (TPU_BASE + 0x10)
-#define TPU_TMDR0 (TPU_BASE + 0x14)
-#define TPU_TIOR0 (TPU_BASE + 0x18)
-#define TPU_TIER0 (TPU_BASE + 0x1C)
-#define TPU_TSR0 (TPU_BASE + 0x20)
-#define TPU_TCNT0 (TPU_BASE + 0x24)
-#define TPU_TGRA0 (TPU_BASE + 0x28)
-#define TPU_TGRB0 (TPU_BASE + 0x2C)
-#define TPU_TGRC0 (TPU_BASE + 0x30)
-#define TPU_TGRD0 (TPU_BASE + 0x34)
-#define TPU_TCR1 (TPU_BASE + 0x50)
-#define TPU_TMDR1 (TPU_BASE + 0x54)
-#define TPU_TIOR1 (TPU_BASE + 0x58)
-#define TPU_TIER1 (TPU_BASE + 0x5C)
-#define TPU_TSR1 (TPU_BASE + 0x60)
-#define TPU_TCNT1 (TPU_BASE + 0x64)
-#define TPU_TGRA1 (TPU_BASE + 0x68)
-#define TPU_TGRB1 (TPU_BASE + 0x6C)
-#define TPU_TGRC1 (TPU_BASE + 0x70)
-#define TPU_TGRD1 (TPU_BASE + 0x74)
-#define TPU_TCR2 (TPU_BASE + 0x90)
-#define TPU_TMDR2 (TPU_BASE + 0x94)
-#define TPU_TIOR2 (TPU_BASE + 0x98)
-#define TPU_TIER2 (TPU_BASE + 0x9C)
-#define TPU_TSR2 (TPU_BASE + 0xB0)
-#define TPU_TCNT2 (TPU_BASE + 0xB4)
-#define TPU_TGRA2 (TPU_BASE + 0xB8)
-#define TPU_TGRB2 (TPU_BASE + 0xBC)
-#define TPU_TGRC2 (TPU_BASE + 0xC0)
-#define TPU_TGRD2 (TPU_BASE + 0xC4)
-#define TPU_TCR3 (TPU_BASE + 0xD0)
-#define TPU_TMDR3 (TPU_BASE + 0xD4)
-#define TPU_TIOR3 (TPU_BASE + 0xD8)
-#define TPU_TIER3 (TPU_BASE + 0xDC)
-#define TPU_TSR3 (TPU_BASE + 0xE0)
-#define TPU_TCNT3 (TPU_BASE + 0xE4)
-#define TPU_TGRA3 (TPU_BASE + 0xE8)
-#define TPU_TGRB3 (TPU_BASE + 0xEC)
-#define TPU_TGRC3 (TPU_BASE + 0xF0)
-#define TPU_TGRD3 (TPU_BASE + 0xF4)
-
-/* CMT */
-
-/* SIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xA4430000
-
-/* SIM */
-
-/* IrDA */
-
-/* IIC */
-
-/* LCDC */
-
-/* USBF */
-
-/* MMCIF */
-
-/* PFC */
-#define PFC_BASE 0xA4050100
-#define PACR (PFC_BASE + 0x00)
-#define PBCR (PFC_BASE + 0x02)
-#define PCCR (PFC_BASE + 0x04)
-#define PDCR (PFC_BASE + 0x06)
-#define PECR (PFC_BASE + 0x08)
-#define PFCR (PFC_BASE + 0x0A)
-#define PGCR (PFC_BASE + 0x0C)
-#define PHCR (PFC_BASE + 0x0E)
-#define PJCR (PFC_BASE + 0x10)
-#define PKCR (PFC_BASE + 0x12)
-#define PLCR (PFC_BASE + 0x14)
-#define PMCR (PFC_BASE + 0x16)
-#define PPCR (PFC_BASE + 0x18)
-#define PRCR (PFC_BASE + 0x1A)
-#define PSCR (PFC_BASE + 0x1C)
-#define PTCR (PFC_BASE + 0x1E)
-#define PUCR (PFC_BASE + 0x20)
-#define PVCR (PFC_BASE + 0x22)
-#define PSELA (PFC_BASE + 0x24)
-#define PSELB (PFC_BASE + 0x26)
-#define PSELC (PFC_BASE + 0x28)
-#define PSELD (PFC_BASE + 0x2A)
-
-/* I/O Port */
-#define PORT_BASE 0xA4050100
-#define PADR (PORT_BASE + 0x40)
-#define PBDR (PORT_BASE + 0x42)
-#define PCDR (PORT_BASE + 0x44)
-#define PDDR (PORT_BASE + 0x46)
-#define PEDR (PORT_BASE + 0x48)
-#define PFDR (PORT_BASE + 0x4A)
-#define PGDR (PORT_BASE + 0x4C)
-#define PHDR (PORT_BASE + 0x4E)
-#define PJDR (PORT_BASE + 0x50)
-#define PKDR (PORT_BASE + 0x52)
-#define PLDR (PORT_BASE + 0x54)
-#define PMDR (PORT_BASE + 0x56)
-#define PPDR (PORT_BASE + 0x58)
-#define PRDR (PORT_BASE + 0x5A)
-#define PSDR (PORT_BASE + 0x5C)
-#define PTDR (PORT_BASE + 0x5E)
-#define PUDR (PORT_BASE + 0x60)
-#define PVDR (PORT_BASE + 0x62)
-
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7720_H_ */
diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig
deleted file mode 100644
index 8331327..0000000
--- a/board/ms7720se/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MS7720SE
-
-config SYS_BOARD
- default "ms7720se"
-
-config SYS_CONFIG_NAME
- default "ms7720se"
-
-endif
diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS
deleted file mode 100644
index 96a80f4..0000000
--- a/board/ms7720se/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MS7720SE BOARD
-M: Yoshihiro Shimoda <yoshihiro.shimoda.uh at renesas.com>
-S: Maintained
-F: board/ms7720se/
-F: include/configs/ms7720se.h
-F: configs/ms7720se_defconfig
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
deleted file mode 100644
index 1819c4c..0000000
--- a/board/ms7720se/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro at renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7720se/Makefile
-#
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y := ms7720se.o
-obj-y += lowlevel_init.o
diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S
deleted file mode 100644
index 3f3d21e..0000000
--- a/board/ms7720se/lowlevel_init.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro at renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write16 WTCSR_A, WTCSR_D
-
- write16 WTCNT_A, WTCNT_D
-
- write16 FRQCR_A, FRQCR_D
-
- write16 UCLKCR_A, UCLKCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS6BBCR_A, CS6BBCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- write32 CS6BWCR_A, CS6BWCR_D
-
- write32 SDCR_A, SDCR_D1
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RTCNT_A RTCNT_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 SDCR_A, SDCR_D2
-
- write16 SDMR3_A, SDMR3_D
-
- write16 PCCR_A, PCCR_D
-
- write16 PDCR_A, PDCR_D
-
- write16 PECR_A, PECR_D
-
- write16 PGCR_A, PGCR_D
-
- write16 PHCR_A, PHCR_D
-
- write16 PPCR_A, PPCR_D
-
- write16 PTCR_A, PTCR_D
-
- write16 PVCR_A, PVCR_D
-
- write16 PSELA_A, PSELA_D
-
- write32 CCR_A, CCR_D
-
- write8 LED_A, LED_D
-
- rts
- nop
-
- .align 4
-
-FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
-WTCNT_A: .long 0xA415FF84
-WTCSR_A: .long 0xA415FF86
-UCLKCR_A: .long 0xA40A0008
-FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
-WTCNT_D: .word 0x5A00
-WTCSR_D: .word 0xA506
-UCLKCR_D: .word 0xA5C0
-
-#define BSC_BASE 0xA4FD0000
-CMNCR_A: .long BSC_BASE
-CS0BCR_A: .long BSC_BASE + 0x04
-CS2BCR_A: .long BSC_BASE + 0x08
-CS3BCR_A: .long BSC_BASE + 0x0C
-CS4BCR_A: .long BSC_BASE + 0x10
-CS5ABCR_A: .long BSC_BASE + 0x14
-CS5BBCR_A: .long BSC_BASE + 0x18
-CS6ABCR_A: .long BSC_BASE + 0x1C
-CS6BBCR_A: .long BSC_BASE + 0x20
-CS0WCR_A: .long BSC_BASE + 0x24
-CS2WCR_A: .long BSC_BASE + 0x28
-CS3WCR_A: .long BSC_BASE + 0x2C
-CS4WCR_A: .long BSC_BASE + 0x30
-CS5AWCR_A: .long BSC_BASE + 0x34
-CS5BWCR_A: .long BSC_BASE + 0x38
-CS6AWCR_A: .long BSC_BASE + 0x3C
-CS6BWCR_A: .long BSC_BASE + 0x40
-SDCR_A: .long BSC_BASE + 0x44
-RTCSR_A: .long BSC_BASE + 0x48
-RTCNT_A: .long BSC_BASE + 0x4C
-RTCOR_A: .long BSC_BASE + 0x50
-SDMR3_A: .long BSC_BASE + 0x58C0
-
-CMNCR_D: .long 0x00000010
-CS0BCR_D: .long 0x36DB0400
-CS2BCR_D: .long 0x36DB0400
-CS3BCR_D: .long 0x36DB4600
-CS4BCR_D: .long 0x36DB0400
-CS5ABCR_D: .long 0x36DB0400
-CS5BBCR_D: .long 0x36DB0200
-CS6ABCR_D: .long 0x36DB0400
-CS6BBCR_D: .long 0x36DB0400
-CS0WCR_D: .long 0x00000B01
-CS2WCR_D: .long 0x00000500
-CS3WCR_D: .long 0x00006D1B
-CS4WCR_D: .long 0x00000500
-CS5AWCR_D: .long 0x00000500
-CS5BWCR_D: .long 0x00000500
-CS6AWCR_D: .long 0x00000500
-CS6BWCR_D: .long 0x00000500
-SDCR_D1: .long 0x00000011
-RTCSR_D: .long 0xA55A0010
-RTCNT_D: .long 0xA55A001F
-RTCOR_D: .long 0xA55A001F
-SDMR3_D: .word 0x0000
-.align 2
-SDCR_D2: .long 0x00000811
-
-#define PFC_BASE 0xA4050100
-PCCR_A: .long PFC_BASE + 0x04
-PDCR_A: .long PFC_BASE + 0x06
-PECR_A: .long PFC_BASE + 0x08
-PGCR_A: .long PFC_BASE + 0x0C
-PHCR_A: .long PFC_BASE + 0x0E
-PPCR_A: .long PFC_BASE + 0x18
-PTCR_A: .long PFC_BASE + 0x1E
-PVCR_A: .long PFC_BASE + 0x22
-PSELA_A: .long PFC_BASE + 0x24
-
-PCCR_D: .word 0x0000
-PDCR_D: .word 0x0000
-PECR_D: .word 0x0000
-PGCR_D: .word 0x0000
-PHCR_D: .word 0x0000
-PPCR_D: .word 0x00AA
-PTCR_D: .word 0x0280
-PVCR_D: .word 0x0000
-PSELA_D: .word 0x0000
-.align 2
-
-CCR_A: .long 0xFFFFFFEC
-!CCR_D: .long 0x0000000D
-CCR_D: .long 0x0000000B
-
-LED_A: .long 0xB6800000
-LED_D: .long 0xFF
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
deleted file mode 100644
index 534a422..0000000
--- a/board/ms7720se/ms7720se.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro at renesas.com>
- *
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/ms7720se/ms7720se.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define LED_BASE 0xB0800000
-
-int checkboard(void)
-{
- puts("BOARD: Hitachi UL MS7720SE\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
- printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
- outw(value & 0xFF, LED_BASE);
-}
diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig
deleted file mode 100644
index 0e3f834..0000000
--- a/configs/ms7720se_defconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_SH=y
-CONFIG_TARGET_MS7720SE=y
diff --git a/doc/README.sh b/doc/README.sh
index 6baee08..eff6be8 100644
--- a/doc/README.sh
+++ b/doc/README.sh
@@ -23,13 +23,10 @@ U-Boot for Renesas SuperH
2.2. Renesas SH7722
This CPU has the SH4AL-DSP core.
- 2.3. Renesas SH7720
- This CPU has the SH3 core.
-
- 2.4. Renesas SH7710/SH7712
+ 2.3. Renesas SH7710/SH7712
This CPU has the SH3-DSP core and Ethernet controller.
- 2.5. Renesas SH7780
+ 2.4. Renesas SH7780
This CPU has the SH4A core.
================================================================================
@@ -54,15 +51,6 @@ U-Boot for Renesas SuperH
- Marubun PCMCIA
- SMC91x ethernet
- 3.2. Hitachi UL MS7720ERP01
- Board specific code is in board/ms7720se
- To use this board, type "make ms7720se_config".
- Support devices are :
- - SCIF
- - SDRAM
- - NOR Flash
- - Marubun PCMCIA
-
3.3. Renesas R7780MP
Board specific code is in board/r7780mp
To use this board, type "make r7780mp_config".
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 8cefa65..5f3473f 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -39,8 +39,7 @@ struct uart_port {
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
*/
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
-#elif defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
+#elif defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372) || \
@@ -284,7 +283,6 @@ struct uart_port {
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
@@ -334,7 +332,6 @@ struct uart_port {
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
@@ -449,7 +446,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
@@ -507,7 +503,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
#endif
#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
@@ -719,7 +714,6 @@ static inline int sci_rxd_in(struct uart_port *port)
!defined(CONFIG_SH_SH2007)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
deleted file mode 100644
index 585d68f..0000000
--- a/include/configs/ms7720se.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Configuation settings for the Hitachi Solution Engine 7720
- *
- * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro at renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MS7720SE_H
-#define __MS7720SE_H
-
-#define CONFIG_CPU_SH7720 1
-#define CONFIG_MS7720SE 1
-
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_BOOTARGS "console=ttySC0,115200"
-#define CONFIG_BOOTFILE "/boot/zImage"
-#define CONFIG_LOADADDR 0x8E000000
-
-#define CONFIG_VERSION_VARIABLE
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define MS7720SE_SDRAM_BASE 0x8C000000
-#define MS7720SE_FLASH_BASE_1 0xA0000000
-#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
-
-#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
-/* Buffer size for Boot Arguments passed to kernel */
-#define CONFIG_SYS_BARGSIZE 512
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_SCIF_CONSOLE 1
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
-
-#define CONFIG_SYS_MAX_FLASH_SECT 150
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
-
-/* PCMCIA */
-#define CONFIG_IDE_PCMCIA 1
-#define CONFIG_MARUBUN_PCCARD 1
-#define CONFIG_PCMCIA_SLOT_A 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
-#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
-#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
-#define CONFIG_SYS_MARUBUN_IO 0xb8600000
-
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-
-#endif /* __MS7720SE_H */
--
1.7.11.5
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