[U-Boot] [PATCH v2] armv8: caches: Added routine to set non cacheable region

Siva Durga Prasad Paladugu siva.durga.paladugu at xilinx.com
Tue May 12 05:46:49 CEST 2015


Hi Mark,


> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Wednesday, April 29, 2015 10:00 PM
> To: Michal Simek
> Cc: u-boot at lists.denx.de; Albert Aribaud; Marek Vasut; Tom Rini; Siva Durga
> Prasad Paladugu; Varun Sethi; Thierry Reding; Arnab Basu; York Sun
> Subject: Re: [U-Boot] [PATCH v2] armv8: caches: Added routine to set non
> cacheable region
> 
> Hi Michal,
> 
> On Wed, Apr 29, 2015 at 09:35:35AM +0100, Michal Simek wrote:
> > Added routine mmu_set_region_dcache_behaviour() to set a particular
> > region as non cacheable.
> 
> What's the intended use of this?
This is intended to mark a dynamically allocated region as non-cacheable region in runtime.
There is same kind of routine for armv7 but not for armv8. Do you think that the same functionality to be addressed for armv8 too? 

As per below comment, you are correct, this looks like to be more board specific.
We may have to move it to some board specific code.

Regards,
Siva

> 
> > Define dummy routine for mmu_set_region_dcache_behaviour() to
> handle
> > incase of dcache off.
> >
> > Signed-off-by: Siva Durga Prasad Paladugu <sivadur at xilinx.com>
> > Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> > ---
> >
> > Changes in v2:
> > - Fix patch subject (remove addional zzz from v1)
> > - Remove armv8: caches: Disable dcache after flush patch from this
> >   series based on the talk with Mark Rutland (patch is not needed
> >   anymore)
> >
> >  arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
> > arch/arm/include/asm/system.h | 28 ++++++++++++++++++----------
> >  2 files changed, 41 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv8/cache_v8.c
> > b/arch/arm/cpu/armv8/cache_v8.c index c5ec5297cd39..25a2136a3cdf
> > 100644
> > --- a/arch/arm/cpu/armv8/cache_v8.c
> > +++ b/arch/arm/cpu/armv8/cache_v8.c
> > @@ -139,6 +139,24 @@ int dcache_status(void)
> >  	return (get_sctlr() & CR_C) != 0;
> >  }
> >
> > +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> > +				     enum dcache_option option)
> > +{
> > +	/* get the level2_table0 start address */
> > +	u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);
> 
> This looks very specific to a particular platform.
> 
> > +	u64 upto, end;
> > +
> > +	end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
> > +	      MMU_SECTION_SHIFT;
> > +	start = start >> MMU_SECTION_SHIFT;
> > +	for (upto = start; upto < end; upto++) {
> > +		page_table[upto] &= ~PMD_ATTRINDX_MASK;
> > +		page_table[upto] |= PMD_ATTRINDX(option);
> > +	}
> > +
> > +	flush_dcache_range(page_table[start], page_table[end]);
> 
> This looks odd. Aren't these the values in the page tables (complete with
> attributes), rather than (virtual) addresses?
> 
> What exactly are you trying to flush here? Depending on your TCR settings
> you don't necessarily have to flush the tables themselves, assuming they
> don't fall inside the region being changed?
> 
> > +	__asm_invalidate_tlb_all();
> 
> If the region was previously cacheable, you'll need to (clean+)invalidate here
> to clear the PA range in the caches.
> 
> Thanks,
> Mark.


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