[U-Boot] wandboard: Switch to SPL support
Vagrant Cascadian
vagrant at aikidev.net
Tue May 12 09:26:57 CEST 2015
On 2015-05-11, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
>
> Currently we need to build one U-boot image for each of the wandboard
> variants: quad, dual-lite and solo.
>
> By switching to SPL we can support all these variants with a single binary,
> which is very convenient.
>
> Based on the work from Richard Hu.
>
> Tested kernel booting on the three boards.
>
> Signed-off-by: Richard Hu <hakahu at gmail.com>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
Tested kernel boot on wandboard quad and dual-lite variants.
Tested-by: Vagrant Cascadian <vagrant at aikidev.net>
> ---
> arch/arm/Kconfig | 1 +
> board/wandboard/MAINTAINERS | 4 +-
> board/wandboard/Makefile | 2 +-
> board/wandboard/README | 22 +--
> board/wandboard/spl.c | 317 +++++++++++++++++++++++++++++++++++++++
> board/wandboard/wandboard.c | 176 ++++++++++++----------
> configs/wandboard_defconfig | 6 +
> configs/wandboard_dl_defconfig | 3 -
> configs/wandboard_quad_defconfig | 3 -
> configs/wandboard_solo_defconfig | 3 -
> include/configs/wandboard.h | 27 ++--
> 11 files changed, 448 insertions(+), 116 deletions(-)
> create mode 100644 board/wandboard/spl.c
> create mode 100644 configs/wandboard_defconfig
> delete mode 100644 configs/wandboard_dl_defconfig
> delete mode 100644 configs/wandboard_quad_defconfig
> delete mode 100644 configs/wandboard_solo_defconfig
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 00be305..ca7448e 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -493,6 +493,7 @@ config TARGET_UDOO
> config TARGET_WANDBOARD
> bool "Support wandboard"
> select CPU_V7
> + select SUPPORT_SPL
>
> config TARGET_WARP
> bool "Support WaRP"
> diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
> index b986980..0680517 100644
> --- a/board/wandboard/MAINTAINERS
> +++ b/board/wandboard/MAINTAINERS
> @@ -3,6 +3,4 @@ M: Fabio Estevam <fabio.estevam at freescale.com>
> S: Maintained
> F: board/wandboard/
> F: include/configs/wandboard.h
> -F: configs/wandboard_dl_defconfig
> -F: configs/wandboard_quad_defconfig
> -F: configs/wandboard_solo_defconfig
> +F: configs/wandboard_defconfig
> diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
> index 5b50eca..db9f4a6 100644
> --- a/board/wandboard/Makefile
> +++ b/board/wandboard/Makefile
> @@ -4,4 +4,4 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y := wandboard.o
> +obj-y := wandboard.o spl.o
> diff --git a/board/wandboard/README b/board/wandboard/README
> index 1f678e1..c6c0132 100644
> --- a/board/wandboard/README
> +++ b/board/wandboard/README
> @@ -12,31 +12,25 @@ http://www.wandboard.org/
> Building U-boot for Wandboard
> -----------------------------
>
> -To build U-Boot for the Wandboard Dual Lite version:
> +To build U-Boot for the Wandboard:
>
> -$ make wandboard_dl_config
> -$ make
> -
> -To build U-Boot for the Wandboard Solo version:
> -
> -$ make wandboard_solo_config
> -$ make
> -
> -To build U-Boot for the Wandboard Quad version:
> -
> -$ make wandboard_quad_config
> +$ make wandboard_config
> $ make
>
> Flashing U-boot into the SD card
> --------------------------------
>
> -- After the 'make' command completes, the generated 'u-boot.imx' binary must be
> +- After the 'make' command completes, the generated 'SPL' binary must be
> flashed into the SD card;
>
> -$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
> +$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
>
> (Note - the SD card node may vary, so adjust this as needed).
>
> +- Flash the u-boot.img image into the SD card:
> +
> +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
> +
> - Insert the SD card into the slot located in the bottom of the board (same side
> as the mx6 processor)
>
> diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
> new file mode 100644
> index 0000000..77afae7
> --- /dev/null
> +++ b/board/wandboard/spl.c
> @@ -0,0 +1,317 @@
> +/*
> + * Copyright (C) 2014 Wandboard
> + * Author: Tungyi Lin <tungyilin1127 at gmail.com>
> + * Richard Hu <hakahu at gmail.com>
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/mx6-pins.h>
> +#include <asm/errno.h>
> +#include <asm/gpio.h>
> +#include <asm/imx-common/iomux-v3.h>
> +#include <asm/imx-common/video.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/io.h>
> +#include <asm/arch/sys_proto.h>
> +#include <spl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_SPL_BUILD)
> +#include <asm/arch/mx6-ddr.h>
> +/*
> + * Driving strength:
> + * 0x30 == 40 Ohm
> + * 0x28 == 48 Ohm
> + */
> +
> +#define IMX6DQ_DRIVE_STRENGTH 0x30
> +#define IMX6SDL_DRIVE_STRENGTH 0x28
> +
> +/* configure MX6Q/DUAL mmdc DDR io registers */
> +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
> + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_cas = IMX6DQ_DRIVE_STRENGTH,
> + .dram_ras = IMX6DQ_DRIVE_STRENGTH,
> + .dram_reset = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdba2 = 0x00000000,
> + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
> + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
> +};
> +
> +/* configure MX6Q/DUAL mmdc GRP io registers */
> +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
> + .grp_ddr_type = 0x000c0000,
> + .grp_ddrmode_ctl = 0x00020000,
> + .grp_ddrpke = 0x00000000,
> + .grp_addds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_ddrmode = 0x00020000,
> + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
> + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
> +};
> +
> +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
> +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
> + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_cas = IMX6SDL_DRIVE_STRENGTH,
> + .dram_ras = IMX6SDL_DRIVE_STRENGTH,
> + .dram_reset = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdba2 = 0x00000000,
> + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
> + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
> +};
> +
> +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
> +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
> + .grp_ddr_type = 0x000c0000,
> + .grp_ddrmode_ctl = 0x00020000,
> + .grp_ddrpke = 0x00000000,
> + .grp_addds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_ddrmode = 0x00020000,
> + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
> + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
> +};
> +
> +/* H5T04G63AFR-PB */
> +static struct mx6_ddr3_cfg h5t04g63afr = {
> + .mem_speed = 1600,
> + .density = 4,
> + .width = 16,
> + .banks = 8,
> + .rowaddr = 15,
> + .coladdr = 10,
> + .pagesz = 2,
> + .trcd = 1375,
> + .trcmin = 4875,
> + .trasmin = 3500,
> +};
> +
> +/* H5TQ2G63DFR-H9 */
> +static struct mx6_ddr3_cfg h5tq2g63dfr = {
> + .mem_speed = 1333,
> + .density = 2,
> + .width = 16,
> + .banks = 8,
> + .rowaddr = 14,
> + .coladdr = 10,
> + .pagesz = 2,
> + .trcd = 1350,
> + .trcmin = 4950,
> + .trasmin = 3600,
> +};
> +
> +static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
> + .p0_mpwldectrl0 = 0x001f001f,
> + .p0_mpwldectrl1 = 0x001f001f,
> + .p1_mpwldectrl0 = 0x001f001f,
> + .p1_mpwldectrl1 = 0x001f001f,
> + .p0_mpdgctrl0 = 0x4301030d,
> + .p0_mpdgctrl1 = 0x03020277,
> + .p1_mpdgctrl0 = 0x4300030a,
> + .p1_mpdgctrl1 = 0x02780248,
> + .p0_mprddlctl = 0x4536393b,
> + .p1_mprddlctl = 0x36353441,
> + .p0_mpwrdlctl = 0x41414743,
> + .p1_mpwrdlctl = 0x462f453f,
> +};
> +
> +/* DDR 64bit 2GB */
> +static struct mx6_ddr_sysinfo mem_q = {
> + .dsize = 2,
> + .cs1_mirror = 0,
> + /* config for full 4GB range so that get_mem_size() works */
> + .cs_density = 32,
> + .ncs = 1,
> + .bi_on = 1,
> + .rtt_nom = 1,
> + .rtt_wr = 0,
> + .ralat = 5,
> + .walat = 0,
> + .mif3_mode = 3,
> + .rst_to_cke = 0x23,
> + .sde_to_rst = 0x10,
> +};
> +
> +static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
> + .p0_mpwldectrl0 = 0x001f001f,
> + .p0_mpwldectrl1 = 0x001f001f,
> + .p1_mpwldectrl0 = 0x001f001f,
> + .p1_mpwldectrl1 = 0x001f001f,
> + .p0_mpdgctrl0 = 0x420e020e,
> + .p0_mpdgctrl1 = 0x02000200,
> + .p1_mpdgctrl0 = 0x42020202,
> + .p1_mpdgctrl1 = 0x01720172,
> + .p0_mprddlctl = 0x494c4f4c,
> + .p1_mprddlctl = 0x4a4c4c49,
> + .p0_mpwrdlctl = 0x3f3f3133,
> + .p1_mpwrdlctl = 0x39373f2e,
> +};
> +
> +static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
> + .p0_mpwldectrl0 = 0x0040003c,
> + .p0_mpwldectrl1 = 0x0032003e,
> + .p0_mpdgctrl0 = 0x42350231,
> + .p0_mpdgctrl1 = 0x021a0218,
> + .p0_mprddlctl = 0x4b4b4e49,
> + .p0_mpwrdlctl = 0x3f3f3035,
> +};
> +
> +/* DDR 64bit 1GB */
> +static struct mx6_ddr_sysinfo mem_dl = {
> + .dsize = 2,
> + .cs1_mirror = 0,
> + /* config for full 4GB range so that get_mem_size() works */
> + .cs_density = 32,
> + .ncs = 1,
> + .bi_on = 1,
> + .rtt_nom = 1,
> + .rtt_wr = 0,
> + .ralat = 5,
> + .walat = 0,
> + .mif3_mode = 3,
> + .rst_to_cke = 0x23,
> + .sde_to_rst = 0x10,
> +};
> +
> +/* DDR 32bit 512MB */
> +static struct mx6_ddr_sysinfo mem_s = {
> + .dsize = 1,
> + .cs1_mirror = 0,
> + /* config for full 4GB range so that get_mem_size() works */
> + .cs_density = 32,
> + .ncs = 1,
> + .bi_on = 1,
> + .rtt_nom = 1,
> + .rtt_wr = 0,
> + .ralat = 5,
> + .walat = 0,
> + .mif3_mode = 3,
> + .rst_to_cke = 0x23,
> + .sde_to_rst = 0x10,
> +};
> +
> +static void ccgr_init(void)
> +{
> + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> + writel(0x00C03F3F, &ccm->CCGR0);
> + writel(0x0030FC03, &ccm->CCGR1);
> + writel(0x0FFFC000, &ccm->CCGR2);
> + writel(0x3FF00000, &ccm->CCGR3);
> + writel(0x00FFF300, &ccm->CCGR4);
> + writel(0x0F0000C3, &ccm->CCGR5);
> + writel(0x000003FF, &ccm->CCGR6);
> +}
> +
> +static void gpr_init(void)
> +{
> + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + /* enable AXI cache for VDOA/VPU/IPU */
> + writel(0xF00000CF, &iomux->gpr[4]);
> + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
> + writel(0x007F007F, &iomux->gpr[6]);
> + writel(0x007F007F, &iomux->gpr[7]);
> +}
> +
> +static void spl_dram_init(void)
> +{
> + if (is_cpu_type(MXC_CPU_MX6SOLO)) {
> + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
> + mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
> + } else if (is_cpu_type(MXC_CPU_MX6DL)) {
> + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
> + mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
> + } else if (is_cpu_type(MXC_CPU_MX6Q)) {
> + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
> + mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
> + }
> +
> + udelay(100);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + ccgr_init();
> +
> + /* setup AIPS and disable watchdog */
> + arch_cpu_init();
> +
> + gpr_init();
> +
> + /* iomux */
> + board_early_init_f();
> +
> + /* setup GP timer */
> + timer_init();
> +
> + /* UART clocks enabled and gd valid - init serial console */
> + preloader_console_init();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +
> + /* Clear the BSS. */
> + memset(__bss_start, 0, __bss_end - __bss_start);
> +
> + /* load/boot image from boot device */
> + board_init_r(NULL, 0);
> +}
> +#endif
> diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
> index 1075c65..90625ab 100644
> --- a/board/wandboard/wandboard.c
> +++ b/board/wandboard/wandboard.c
> @@ -53,66 +53,66 @@ DECLARE_GLOBAL_DATA_PTR;
>
> int dram_init(void)
> {
> - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
> + gd->ram_size = imx_ddr_size();
>
> return 0;
> }
>
> static iomux_v3_cfg_t const uart1_pads[] = {
> - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
> + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
> };
>
> static iomux_v3_cfg_t const usdhc1_pads[] = {
> - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> /* Carrier MicroSD Card Detect */
> - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> };
>
> static iomux_v3_cfg_t const usdhc3_pads[] = {
> - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
> + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> /* SOM MicroSD Card Detect */
> - MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> };
>
> static iomux_v3_cfg_t const enet_pads[] = {
> - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
> + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
> /* AR8031 PHY Reset */
> - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
> + IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> };
>
> static void setup_iomux_uart(void)
> {
> - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
> + SETUP_IOMUX_PADS(uart1_pads);
> }
>
> static void setup_iomux_enet(void)
> {
> - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
> + SETUP_IOMUX_PADS(enet_pads);
>
> /* Reset AR8031 PHY */
> gpio_direction_output(ETH_PHY_RESET, 0);
> @@ -156,15 +156,13 @@ int board_mmc_init(bd_t *bis)
> for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
> switch (index) {
> case 0:
> - imx_iomux_v3_setup_multiple_pads(
> - usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> + SETUP_IOMUX_PADS(usdhc3_pads);
> usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> usdhc_cfg[0].max_bus_width = 4;
> gpio_direction_input(USDHC3_CD_GPIO);
> break;
> case 1:
> - imx_iomux_v3_setup_multiple_pads(
> - usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
> + SETUP_IOMUX_PADS(usdhc1_pads);
> usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
> usdhc_cfg[1].max_bus_width = 4;
> gpio_direction_input(USDHC1_CD_GPIO);
> @@ -218,54 +216,66 @@ int board_phy_config(struct phy_device *phydev)
> }
>
> #if defined(CONFIG_VIDEO_IPUV3)
> -struct i2c_pads_info i2c2_pad_info = {
> +struct i2c_pads_info mx6q_i2c2_pad_info = {
> .scl = {
> - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
> + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
> | MUX_PAD_CTRL(I2C_PAD_CTRL),
> - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
> + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
> | MUX_PAD_CTRL(I2C_PAD_CTRL),
> .gp = IMX_GPIO_NR(4, 12)
> },
> .sda = {
> - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
> + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
> | MUX_PAD_CTRL(I2C_PAD_CTRL),
> - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
> + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(4, 13)
> + }
> +};
> +
> +struct i2c_pads_info mx6dl_i2c2_pad_info = {
> + .scl = {
> + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gp = IMX_GPIO_NR(4, 12)
> + },
> + .sda = {
> + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
> + | MUX_PAD_CTRL(I2C_PAD_CTRL),
> + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
> | MUX_PAD_CTRL(I2C_PAD_CTRL),
> .gp = IMX_GPIO_NR(4, 13)
> }
> };
>
> static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
> - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
> - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
> - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
> - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
> - | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
> - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
> -
> - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
> - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
> - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
> - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
> - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
> - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
> - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
> - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
> - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
> - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
> - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
> - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
> - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
> - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
> - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
> - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
> - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
> - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
> -
> - MX6_PAD_SD4_DAT2__GPIO2_IO10
> - | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
> - MX6_PAD_SD4_DAT3__GPIO2_IO11
> - | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
> + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
> + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
> + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
> + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
> + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
> + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
> + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
> + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
> + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
> + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
> + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
> + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
> + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
> + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
> + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
> + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
> + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
> + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
> + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
> + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
> + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
> + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
> + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
> + IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
> + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
> };
>
> static void do_enable_hdmi(struct display_info_t const *dev)
> @@ -281,9 +291,7 @@ static int detect_i2c(struct display_info_t const *dev)
>
> static void enable_fwadapt_7wvga(struct display_info_t const *dev)
> {
> - imx_iomux_v3_setup_multiple_pads(
> - fwadapt_7wvga_pads,
> - ARRAY_SIZE(fwadapt_7wvga_pads));
> + SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
>
> gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
> gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
> @@ -346,7 +354,7 @@ static void setup_display(void)
> writel(reg, &mxc_ccm->chsccdr);
>
> /* Disable LCD backlight */
> - imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
> + SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
> gpio_direction_input(IMX_GPIO_NR(4, 20));
> }
> #endif /* CONFIG_VIDEO_IPUV3 */
> @@ -391,6 +399,12 @@ int board_late_init(void)
> add_board_boot_modes(board_boot_modes);
> #endif
>
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> + setenv("board_rev", "MX6Q");
> + else
> + setenv("board_rev", "MX6DL");
> +#endif
> return 0;
> }
>
> @@ -399,7 +413,11 @@ int board_init(void)
> /* address of boot parameters */
> gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
> + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
> + else
> + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
>
> return 0;
> }
> diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
> new file mode 100644
> index 0000000..1ccac5a
> --- /dev/null
> +++ b/configs/wandboard_defconfig
> @@ -0,0 +1,6 @@
> +CONFIG_SPL=y
> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
> +CONFIG_ARM=y
> +CONFIG_TARGET_WANDBOARD=y
> +CONFIG_DM=y
> +CONFIG_DM_THERMAL=y
> diff --git a/configs/wandboard_dl_defconfig b/configs/wandboard_dl_defconfig
> deleted file mode 100644
> index 5a1f7f5..0000000
> --- a/configs/wandboard_dl_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
> -CONFIG_ARM=y
> -CONFIG_TARGET_WANDBOARD=y
> diff --git a/configs/wandboard_quad_defconfig b/configs/wandboard_quad_defconfig
> deleted file mode 100644
> index d940848..0000000
> --- a/configs/wandboard_quad_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
> -CONFIG_ARM=y
> -CONFIG_TARGET_WANDBOARD=y
> diff --git a/configs/wandboard_solo_defconfig b/configs/wandboard_solo_defconfig
> deleted file mode 100644
> index 66aa5d3..0000000
> --- a/configs/wandboard_solo_defconfig
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
> -CONFIG_ARM=y
> -CONFIG_TARGET_WANDBOARD=y
> diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
> index b2c3614..7ce861e 100644
> --- a/include/configs/wandboard.h
> +++ b/include/configs/wandboard.h
> @@ -14,6 +14,10 @@
> #include <asm/imx-common/gpio.h>
> #include <linux/sizes.h>
>
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_MMC_SUPPORT
> +#include "imx6_spl.h"
> +
> #define CONFIG_MX6
> #define CONFIG_DISPLAY_CPUINFO
> #define CONFIG_DISPLAY_BOARDINFO
> @@ -125,20 +129,15 @@
> #define CONFIG_MXC_OCOTP
> #endif
>
> -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
> -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
> -#elif defined(CONFIG_MX6Q)
> -#define CONFIG_DEFAULT_FDT_FILE "imx6q-wandboard.dtb"
> -#endif
> -
> +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> #define CONFIG_EXTRA_ENV_SETTINGS \
> "script=boot.scr\0" \
> "image=zImage\0" \
> "console=ttymxc0\0" \
> "splashpos=m,m\0" \
> + "fdtfile=undefined\0" \
> "fdt_high=0xffffffff\0" \
> "initrd_high=0xffffffff\0" \
> - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> "fdt_addr=0x18000000\0" \
> "boot_fdt=try\0" \
> "ip_dyn=yes\0" \
> @@ -192,7 +191,7 @@
> "bootscript=echo Running bootscript from mmc ...; " \
> "source\0" \
> "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
> - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
> + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
> "mmcboot=echo Booting from mmc ...; " \
> "run mmcargs; " \
> "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> @@ -220,7 +219,7 @@
> "fi; " \
> "${get_cmd} ${image}; " \
> "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
> - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
> + "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
> "bootz ${loadaddr} - ${fdt_addr}; " \
> "else " \
> "if test ${boot_fdt} = try; then " \
> @@ -231,9 +230,17 @@
> "fi; " \
> "else " \
> "bootz; " \
> - "fi;\0"
> + "fi;\0" \
> + "findfdt="\
> + "if test $board_rev = MX6Q ; then " \
> + "setenv fdtfile imx6q-wandboard.dtb; fi; " \
> + "if test $board_rev = MX6DL ; then " \
> + "setenv fdtfile imx6dl-wandboard.dtb; fi; " \
> + "if test $fdtfile = undefined; then " \
> + "echo WARNING: Could not determine dtb to use; fi; \0" \
>
> #define CONFIG_BOOTCOMMAND \
> + "run findfdt; " \
> "mmc dev ${mmcdev}; if mmc rescan; then " \
> "if run loadbootscript; then " \
> "run bootscript; " \
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