[U-Boot] [PATCH v2 04/16] tegra: spi: Support slow SPI rates
Simon Glass
sjg at chromium.org
Wed May 13 15:45:48 CEST 2015
Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v2: None
drivers/spi/tegra114_spi.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 0d69376..d7eecd5 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -144,6 +144,7 @@ static int tegra114_spi_probe(struct udevice *bus)
struct tegra_spi_platdata *plat = dev_get_platdata(bus);
struct tegra114_spi_priv *priv = dev_get_priv(bus);
struct spi_regs *regs;
+ ulong rate;
priv->regs = (struct spi_regs *)plat->base;
regs = priv->regs;
@@ -152,9 +153,20 @@ static int tegra114_spi_probe(struct udevice *bus)
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
- /* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
- priv->freq);
+ /*
+ * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
+ * back to the oscillator if that is too fast.
+ */
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+ if (rate > priv->freq + 100000) {
+ rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
+ priv->freq);
+ if (rate != priv->freq) {
+ printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
+ bus->name, priv->freq, rate);
+ }
+ }
/* Clear stale status here */
setbits_le32(®s->fifo_status,
--
2.2.0.rc0.207.ga3a616c
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