[U-Boot] [PATCH] ls1021atwr: added deep sleep support in uboot

[Yuantian.Tang at freescale.com]

From: Tang Yuantian <Yuantian.Tang at freescale.com>

Signed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com>
---
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++
 board/freescale/ls1021atwr/ls1021atwr.c           | 68 ++++++++++++++++++++++-
 include/configs/ls1021atwr.h                      |  7 ++-
 3 files changed, 75 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index a8122c1..bbd5955 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -370,6 +370,10 @@ struct ccsr_serdes {
 #define DDR_DDR_ZQ_CNTL			0x89080600
 #define DDR_CS0_CONFIG_2		0
 #define DDR_SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN	0x00000080
+#define SDRAM_CFG2_FRC_SR		0x80000000
+#define SDRAM_CFG_BI			0x00000001
 
 /* DDR memory controller registers */
 struct ccsr_ddr {
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index ed5bd27..2c8d6d1 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -21,6 +21,7 @@
 #include <tsec.h>
 #include <fsl_sec.h>
 #include <spl.h>
+#include "../common/sleep.h"
 #ifdef CONFIG_U_QE
 #include "../../../drivers/qe/qe.h"
 #endif
@@ -147,6 +148,7 @@ unsigned int get_soc_major_rev(void)
 void ddrmc_init(void)
 {
 	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg;
 
 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 
@@ -160,7 +162,22 @@ void ddrmc_init(void)
 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 
-	out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		out_be32(&ddr->sdram_cfg_2,
+			 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+		out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+		out_be32(&ddr->init_ext_addr, (1 << 31));
+
+		/* DRAM VRef will not be trained */
+		out_be32(&ddr->ddr_cdr2,
+			 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+	} else
+#endif
+	{
+		out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+		out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+	}
 
 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
@@ -173,14 +190,35 @@ void ddrmc_init(void)
 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 
 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
-	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 
 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 
 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 	udelay(1);
-	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* enter self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+	} else
+#endif
+		temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot()) {
+		/* exit self-refresh */
+		temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+		temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+		out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+	}
+#endif
 }
 
 int dram_init(void)
@@ -190,6 +228,11 @@ int dram_init(void)
 #endif
 
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
 	return 0;
 }
 
@@ -384,6 +427,11 @@ int board_early_init_f(void)
 		out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 	}
 
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
 	return 0;
 }
 
@@ -395,6 +443,11 @@ void board_init_f(ulong dummy)
 
 	get_clocks();
 
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
 	preloader_console_init();
 
 	dram_init();
@@ -563,6 +616,15 @@ int misc_init_r(void)
 }
 #endif
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LS102XA_NS_ACCESS
+	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 729205f..4b96feb 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -18,6 +18,10 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DEEP_SLEEP
+#ifdef CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+#endif
 
 /*
  * Size of malloc() pool
@@ -60,7 +64,8 @@
 #define CONFIG_SPL_PAD_TO		0x1c000
 #define CONFIG_SYS_TEXT_BASE		0x82000000
 
-#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+		CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
-- 
2.1.0.27.g96db324