[U-Boot] [PATCH 2/2] sunxi: Cache line size definition

[Paul Kocialkowski]

Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores,
which all have 64 bytes cache line size.

This is required to e.g. enable USB gadget.

Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 include/configs/sunxi-common.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 723067e..3e4e26b 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -66,6 +66,9 @@
 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 
+/* CPU */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
-- 
1.9.1