[U-Boot] [PATCH 3/3] x86: quark: Implement PIRQ routing

[Bin Meng]

Hi Simon,

On Tue, May 5, 2015 at 10:05 AM, Simon Glass <sjg at chromium.org> wrote:
> Hi Bin,
>
> On 4 May 2015 at 00:27, Bin Meng <bmeng.cn at gmail.com> wrote:
>>
>> Hi Simon,
>>
>> On Tue, Apr 28, 2015 at 10:05 PM, Simon Glass <sjg at chromium.org> wrote:
>> > Hi Bin,
>> >
>> > On 27 April 2015 at 00:16, Bin Meng <bmeng.cn at gmail.com> wrote:
>> >> Intel Quark SoC has the same interrupt routing mechanism as the
>> >> Queensbay platform, only the difference is that PCI devices'
>> >> INTA/B/C/D are harcoded and cannot be changed freely.
>> >>
>> >> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>> >>
>> >> ---
>> >>
>> >>  arch/x86/cpu/quark/Makefile              |   2 +-
>> >>  arch/x86/cpu/quark/irq.c                 | 173 +++++++++++++++++++++++++++++++
>> >>  arch/x86/cpu/quark/quark.c               |   8 ++
>> >>  arch/x86/include/asm/arch-quark/device.h |  70 ++++++++++---
>> >>  arch/x86/include/asm/arch-quark/irq.h    |  55 ++++++++++
>> >>  arch/x86/include/asm/arch-quark/quark.h  |  15 +++
>> >>  configs/galileo_defconfig                |   1 +
>> >>  include/configs/galileo.h                |   1 +
>> >>  8 files changed, 309 insertions(+), 16 deletions(-)
>> >>  create mode 100644 arch/x86/cpu/quark/irq.c
>> >>  create mode 100644 arch/x86/include/asm/arch-quark/irq.h
>> >
>> > Before going too far down this path I'd like to see if we can put the
>> > IRQ data in the device tree. What do you think?
>> >
>>
>> Device tree might work, and we might come up with a standard intel irq
>> router driver to configure this based on device tree input. But I will
>> need study more chipset datasheet to do that.
>
> OK let's wait for that. It does seem like a job for device tree. Even
> if we can get a binding that works for modern chips that would be a
> win. Let me know what you find.
>

I've refactored current PIRQ support using device tree on queensbay.
Next is on quark and qemu. A patch will be sent out soon.

Regards,
Bin