[U-Boot] [PATCH 3/4] x86: quark: Implement PIRQ routing

[Simon Glass]

On 20 May 2015 at 01:55, Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Intel Quark SoC has the same interrupt routing mechanism as the
> Queensbay platform, only the difference is that PCI devices'
> INTA/B/C/D are harcoded and cannot be changed freely.
>
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>
> ---
>
>  arch/x86/cpu/quark/quark.c               | 31 ++++++++++++++
>  arch/x86/dts/galileo.dts                 | 22 ++++++++++
>  arch/x86/include/asm/arch-quark/device.h | 70 +++++++++++++++++++++++++-------
>  arch/x86/include/asm/arch-quark/quark.h  | 15 +++++++
>  configs/galileo_defconfig                |  1 +
>  include/configs/galileo.h                |  1 +
>  6 files changed, 125 insertions(+), 15 deletions(-)

Acked-by: Simon Glass <sjg at chromium.org>