[U-Boot] [PATCH v2 2/2] x86: qemu: Turn on legacy segments decode

[Bin Meng]

By default the legacy segments C/D/E/F do not decode to system RAM.
Turn on the decode via Programmable Attribute Map (PAM) registers
so that we can write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
Acked-by: Simon Glass <sjg at chromium.org>

---

Changes in v2: None

 arch/x86/cpu/qemu/pci.c               | 20 ++++++++++++++++++++
 arch/x86/include/asm/arch-qemu/qemu.h |  6 ++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c
index ac9c056..2f4ba17 100644
--- a/arch/x86/cpu/qemu/pci.c
+++ b/arch/x86/cpu/qemu/pci.c
@@ -7,6 +7,8 @@
 #include <common.h>
 #include <pci.h>
 #include <pci_rom.h>
+#include <asm/pci.h>
+#include <asm/arch/qemu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +52,8 @@ int board_pci_post_scan(struct pci_controller *hose)
 	ulong start;
 	pci_dev_t bdf;
 	struct pci_device_id graphic_card[] = { { 0x1234, 0x1111 } };
+	u16 device;
+	int pam, i;
 
 	/*
 	 * QEMU emulated graphic card shows in the PCI configuration space with
@@ -67,5 +71,21 @@ int board_pci_post_scan(struct pci_controller *hose)
 		debug("BIOS ran in %lums\n", get_timer(start));
 	}
 
+	/*
+	 * i440FX and Q35 chipset have different PAM register offset, but with
+	 * the same bitfield layout. Here we determine the offset based on its
+	 * PCI device ID.
+	 */
+	device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
+	pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
+
+	/*
+	 * Initialize Programmable Attribute Map (PAM) Registers
+	 *
+	 * Configure legacy segments C/D/E/F to system RAM
+	 */
+	for (i = 0; i < PAM_NUM; i++)
+		x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
+
 	return ret;
 }
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
index 8d7e986..7a9901d 100644
--- a/arch/x86/include/asm/arch-qemu/qemu.h
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -7,6 +7,12 @@
 #ifndef _ARCH_QEMU_H_
 #define _ARCH_QEMU_H_
 
+/* Programmable Attribute Map (PAM) Registers */
+#define I440FX_PAM		0x59
+#define Q35_PAM			0x90
+#define PAM_NUM			7
+#define PAM_RW			0x33
+
 /* I/O Ports */
 #define CMOS_ADDR_PORT		0x70
 #define CMOS_DATA_PORT		0x71
-- 
1.8.2.1