[U-Boot] [PATCH 7/8] ARM: sunxi: Share sun6i PSCI backend with sun8i

[Chen-Yu Tsai]

sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.

Signed-off-by: Chen-Yu Tsai <wens at csie.org>
---
 arch/arm/cpu/armv7/sunxi/Makefile     | 1 +
 arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 4b783e0..76c7e55 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -37,6 +37,7 @@ ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
 obj-$(CONFIG_MACH_SUN6I)	+= psci_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= psci_sun7i.o
+obj-$(CONFIG_MACH_SUN8I)	+= psci_sun6i.o
 endif
 endif
 
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index 2516804..d4cb51e 100644
--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
@@ -124,11 +124,13 @@ psci_fiq_enter:
 	str	r10, [r8, #0x100]
 	timer_wait r10, ONE_MS
 
+#ifdef CONFIG_MACH_SUN6I
 	@ Activate power clamp
 	lsl	r12, r9, #2		@ x4
 	add	r12, r12, r8
 	mov	r10, #0xff
 	str	r10, [r12, #0x140]
+#endif
 
 	movw	r8, #(SUN6I_CPUCFG_BASE & 0xffff)
 	movt	r8, #(SUN6I_CPUCFG_BASE >> 16)
@@ -186,6 +188,7 @@ psci_cpu_on:
 	movw	r0, #(SUNXI_PRCM_BASE & 0xffff)
 	movt	r0, #(SUNXI_PRCM_BASE >> 16)
 
+#ifdef CONFIG_MACH_SUN6I
 	@ Release power clamp
 	lsl	r5, r1, #2	@ 1 register per CPU
 	add	r5, r5, r0	@ PRCM
@@ -194,6 +197,7 @@ psci_cpu_on:
 1:	lsrs	r6, r6, #1
 	str	r6, [r5, #0x140] @ CPUx_PWR_CLAMP
 	bne	1b
+#endif
 
 	timer_wait r6, TEN_MS
 
-- 
2.1.4