[U-Boot] [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support

Gong Qianyu Qianyu.Gong at freescale.com
Mon Nov 2 12:15:45 CET 2015


Reuse dts files from ls1043a linux kernel. Some parts in dts files
may not be needed by U-Boot.

Signed-off-by: Gong Qianyu <Qianyu.Gong at freescale.com>
---
V2:
 - New Patch.

 arch/arm/dts/Makefile            |   1 +
 arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++++++++++++++++++
 arch/arm/dts/fsl-ls1043a.dtsi    | 346 +++++++++++++++++++++++++++++++++++++++
 configs/ls1043ardb_defconfig     |   2 +
 4 files changed, 518 insertions(+)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ddc6a05..3f3a739 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
 	ls1021a-twr.dtb
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
 	fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
 
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
new file mode 100644
index 0000000..51b5e9f
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -0,0 +1,169 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu at freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+	model = "LS1043A RDB Board";
+};
+
+&i2c0 {
+	status = "okay";
+	ina220 at 40 {
+		compatible = "ti,ina220";
+		reg = <0x40>;
+		shunt-resistor = <1000>;
+	};
+	adt7461a at 4c {
+		compatible = "adt7461a";
+		reg = <0x4c>;
+	};
+	eeprom at 56 {
+		compatible = "at24,24c512";
+		reg = <0x52>;
+	};
+
+	eeprom at 57 {
+		compatible = "at24,24c512";
+		reg = <0x53>;
+	};
+
+	rtc at 68 {
+		compatible = "pericom,pt7c4338";
+		reg = <0x68>;
+	};
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, NAND Flashes and FPGA on board */
+	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+		  0x2 0x0 0x0 0x7e800000 0x00010000
+		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+		nor at 0,0 {
+			compatible = "cfi-flash";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partition at 0 {
+				/* 1MB for RCW and PBI Image */
+				reg = <0x00000000 0x00100000>;
+				label = "NOR bank0 RCW Image";
+			};
+
+			partition at 100000 {
+				/* 1MB for bank0 u-boot Image */
+				reg = <0x00100000 0x00100000>;
+				label = "NOR bank0 U-Boot Image";
+			};
+
+			partition at 200000 {
+				/* 1 MB for bank0 u-boot Env */
+				reg = <0x00200000 0x00100000>;
+				label = "NOR bank0 U-Boot Env";
+			};
+
+			partition at 300000 {
+				/* 1MB for FMan ucode */
+				reg = <0x00300000 0x00100000>;
+				label = "NOR bank0 FMan ucode";
+			};
+
+			partition at 1100000 {
+				/* 40MB for bank0 FIT Image */
+				reg = <0x01100000 0x2800000>;
+				label = "NOR bank0 FIT Image";
+			};
+
+			partition at 4000000 {
+				/* 1MB for bank4 RCW and PBI Image */
+				reg = <0x04000000 0x100000>;
+				label = "NOR bank4 RCW Image";
+			};
+
+			partition at 4100000 {
+				/* 1MB for bank4 u-boot Image */
+				reg = <0x04100000 0x100000>;
+				label = "NOR bank4 U-Boot Image";
+			};
+
+			partition at 4200000 {
+				/* 1 MB for bank4 u-boot Env */
+				reg = <0x04200000 0x100000>;
+				label = "NOR bank4 U-Boot Env";
+			};
+
+			partition at 4300000 {
+				/* 1 MB for bank4 FMan ucode */
+				reg = <0x04300000 0x100000>;
+				label = "NOR bank4 FMan ucode";
+			};
+
+			partition at 5100000 {
+				/* 40MB for bank4 FIT Image */
+				reg = <0x05100000 0x2800000>;
+				label = "NOR bank4 FIT Image";
+			};
+		};
+
+		nand at 1,0 {
+			compatible = "fsl,ifc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x2 0x0 0x10000>;
+
+			partition at 0 {
+				/* This location must not be altered  */
+				/* 1MB for u-boot Bootloader Image */
+				reg = <0x0 0x00100000>;
+				label = "NAND U-Boot Image";
+				read-only;
+			};
+
+			partition at 140000 {
+				/* 1MB for DTB Image */
+				reg = <0x00140000 0x002000>;
+				label = "NAND U-Boot Env";
+			};
+
+			partition at 200000 {
+				/* 20MB for FIT Image */
+				reg = <0x00200000 0x01400000>;
+				label = "NAND FIT Image";
+			};
+		};
+
+		cpld: board-control at 2,0 {
+			compatible = "fsl,ls1043ardb-cpld", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x2 0x0 0x0000100>;
+			bank-width = <1>;
+			device-width = <1>;
+			ranges = <0 2 0 0x100>;
+		};
+};
+
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
new file mode 100644
index 0000000..3d34837
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -0,0 +1,346 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu at freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+	compatible = "fsl,ls1043a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			clocks = <&cluster1_clk>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			clocks = <&cluster1_clk>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			clocks = <&cluster1_clk>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			clocks = <&cluster1_clk>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0x1>, /* Physical Secure PPI */
+			     <1 14 0x1>, /* Physical Non-Secure PPI */
+			     <1 11 0x1>, /* Virtual PPI */
+			     <1 10 0x1>; /* Hypervisor PPI */
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0 106 0x4>,
+			     <0 107 0x4>,
+			     <0 95 0x4>,
+			     <0 97 0x4>;
+	};
+
+	gic: interrupt-controller at 1400000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+		      <0x0 0x1402000 0 0x1000>, /* GICC */
+		      <0x0 0x1404000 0 0x2000>, /* GICH */
+		      <0x0 0x1406000 0 0x2000>; /* GICV */
+		interrupts = <1 9 0xf08>;
+	};
+
+	msi1: msi-controller1 at 1571000 {
+		compatible = "fsl,1s1043a-msi";
+		reg = <0x0 0x1571000 0x0 0x4>,
+		      <0x0 0x1571004 0x0 0x4>;
+		reg-names = "msiir", "msir";
+		msi-controller;
+		interrupts = <0 116 0x4>;
+	};
+
+	msi2: msi-controller2 at 1572000 {
+		compatible = "fsl,1s1043a-msi";
+		reg = <0x0 0x1572000 0x0 0x4>,
+		      <0x0 0x1572004 0x0 0x4>;
+		reg-names = "msiir", "msir";
+		msi-controller;
+		interrupts = <0 126 0x4>;
+	};
+
+	msi3: msi-controller3 at 1573000 {
+		compatible = "fsl,1s1043a-msi";
+		reg = <0x0 0x1573000 0x0 0x4>,
+		      <0x0 0x1573004 0x0 0x4>;
+		reg-names = "msiir", "msir";
+		msi-controller;
+		interrupts = <0 160 0x4>;
+	};
+
+	tzasc: tzasc at 1500000 {
+		reg = <0x0 0x1500000 0x0 0x10000>;
+		interrupts = <0 93 0x4>;
+		status = "disabled";
+	};
+
+	ifc: ifc at 1530000 {
+		compatible = "fsl,ifc", "simple-bus";
+		reg = <0x0 0x1530000 0x0 0x10000>;
+		interrupts = <0 43 0x4>;
+	};
+
+	sfp: sfp at 1e80000 {
+		reg = <0x00 0x1e80000 0x0 0x10000>;
+		status = "disabled";
+	};
+
+	snvs: snvs at 1e90000 {
+		reg = <0x00 0x1e90000 0x0 0x10000>;
+		status = "disabled";
+	};
+
+	serdes1: serdes1 at 1ea0000 {
+		reg = <0x00 0x1ea0000 0x0 0x10000>;
+		status = "disabled";
+	};
+
+	clockgen: clocking at 1ee1000 {
+		ranges = <0x0 0x0 0x1ee1000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		sysclk: sysclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "sysclk";
+		};
+
+		cga_pll1: pll1 at 800 {
+			compatible = "fsl,qoriq-core-pll-2.0";
+			#clock-cells = <1>;
+			reg = <0x800 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cga-pll1", "cga-pll1-div2",
+					"cga-pll1-div3", "cga-pll1-div4";
+		};
+
+		cga_pll2: pll2 at 820 {
+			compatible = "fsl,qoriq-core-pll-2.0";
+			#clock-cells = <1>;
+			reg = <0x820 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cga-pll2", "cga-pll2-div2",
+					"cga-pll2-div3", "cga-pll2-div4";
+		};
+
+		platform_clk: pll at c00 {
+			compatible = "fsl,qoriq-core-pll-2.0";
+			#clock-cells = <1>;
+			reg = <0xc00 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "platform-clk", "platform-clk-div2";
+		};
+
+		cluster1_clk: clk0c0 at 0 {
+			compatible = "fsl,qoriq-core-mux-2.0";
+			#clock-cells = <0>;
+			reg = <0x0 0x10>;
+			clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4",
+				      "pll2cga", "pll2cga-div2", "pll2cga-div4";
+			clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>,
+				 <&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2 2>;
+			clock-output-names = "cluster1-clk";
+
+		};
+	};
+
+	i2c0: i2c at 2180000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2180000 0x0 0x10000>;
+		interrupts = <0 56 0x4>;
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+		status = "disabled";
+	};
+
+	i2c1: i2c at 2190000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2190000 0x0 0x10000>;
+		interrupts = <0 57 0x4>;
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+		status = "disabled";
+	};
+
+	i2c2: i2c at 21a0000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x21a0000 0x0 0x10000>;
+		interrupts = <0 58 0x4>;
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+		status = "disabled";
+	};
+
+	i2c3: i2c at 21b0000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x21b0000 0x0 0x10000>;
+		interrupts = <0 59 0x4>;
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+		status = "disabled";
+	};
+
+	duart0: serial at 21c0500 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x00 0x21c0500 0x0 0x100>;
+		interrupts = <0 54 0x4>;
+		clock-frequency = <400000000>;
+	};
+
+	duart1: serial at 21c0600 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x00 0x21c0600 0x0 0x100>;
+		interrupts = <0 54 0x4>;
+		clock-frequency = <400000000>;
+	};
+
+	duart2: serial at 21d0500 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21d0500 0x0 0x100>;
+		interrupts = <0 55 0x4>;
+		clock-frequency = <400000000>;
+	};
+
+	duart3: serial at 21d0600 {
+		device_type = "serial";
+		compatible = "fsl,ns16550", "ns16550a";
+		reg = <0x0 0x21d0600 0x0 0x100>;
+		interrupts = <0 55 0x4>;
+		clock-frequency = <400000000>;
+	};
+
+	pcie at 3400000 {
+		compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 118 0x4>, /* controller interrupt */
+			     <0 117 0x4>; /* PME interrupt */
+		interrupt-names = "intr", "pme";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		msi-parent = <&msi1>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+				<0000 0 0 2 &gic 0 111 0x4>,
+				<0000 0 0 3 &gic 0 112 0x4>,
+				<0000 0 0 4 &gic 0 113 0x4>;
+	};
+
+	pcie at 3500000 {
+		compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+		       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 128 0x4>,
+			     <0 127 0x4>;
+		interrupt-names = "intr", "pme";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		msi-parent = <&msi2>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
+				<0000 0 0 2 &gic 0 121 0x4>,
+				<0000 0 0 3 &gic 0 122 0x4>,
+				<0000 0 0 4 &gic 0 123 0x4>;
+	};
+
+	pcie at 3600000 {
+		compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+		       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 162 0x4>,
+			     <0 161 0x4>;
+		interrupt-names = "intr", "pme";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		msi-parent = <&msi3>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+				<0000 0 0 2 &gic 0 155 0x4>,
+				<0000 0 0 3 &gic 0 156 0x4>,
+				<0000 0 0 4 &gic 0 157 0x4>;
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0 0x80000000>;
+		      /* DRAM space 1 - 2 GB DRAM */
+	};
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+	};
+};
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index ae84d2e..f77fbbf 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -2,3 +2,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043ARDB=y
 CONFIG_FSL_LAYERSCAPE=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
-- 
2.1.0.27.g96db324



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