[U-Boot] [PATCH 5/5] LS102XA:workaround:disable priorities within DDR

[York Sun]

On 10/21/2015 03:14 AM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
> 
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on Rev2.0.
> 
> Signed-off-by: Yuan Yao <yao.yuan at freescale.com>
> ---
>  arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
> index b15cd60..98d4acd 100644
> --- a/arch/arm/cpu/armv7/ls102xa/soc.c
> +++ b/arch/arm/cpu/armv7/ls102xa/soc.c
> @@ -25,7 +25,7 @@ int arch_soc_init(void)
>  {
>  	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>  	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
> -	unsigned int major;
> +	unsigned int major, reg;
>  
>  #ifdef CONFIG_FSL_QSPI
>  	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
> @@ -86,5 +86,16 @@ int arch_soc_init(void)
>  	 */
>  	out_be32(&scfg->eddrtqcfg, 0x63b20002);
>  
> +	/*
> +	 * EDDRTQCFG Registers are Integration Strap values which controls
> +	 * performance parameters for DDR Controller.
> +	 * The bit 25 is used for disable priorities within DDR.
> +	 * This is a workaround because of the DDR are connected backwards
> +	 * on Rev2.0.
> +	 */

Is there an erratum number for this? If not, please be specific about rev 2.0.
Is it SoC version, or something else?

York