[U-Boot] [Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT register access
Scott Wood
scottwood at freescale.com
Thu Nov 5 00:45:28 CET 2015
On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 4cee038..8471678 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -13,6 +13,7 @@
> #include <malloc.h>
> #ifdef CONFIG_FSL_LAYERSCAPE
> #include <asm/arch/fdt.h>
> +#include <asm/arch/soc.h>
> #endif
>
> #ifndef CONFIG_SYS_PCI_MEMORY_BUS
> @@ -57,11 +58,6 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> -/* LUT registers */
> -#define PCIE_LUT_BASE 0x80000
> -#define PCIE_LUT_LCTRL0 0x7F8
> -#define PCIE_LUT_DBG 0x7FC
> -
> #define PCIE_DBI_RO_WR_EN 0x8bc
>
> #define PCIE_LINK_CAP 0x7c
> @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
>
> return 1;
> }
> -#else
> +#elif defined(CONFIG_FSL_LAYERSCAPE)
> static int ls_pcie_link_state(struct ls_pcie *pcie)
> {
> u32 state;
>
> - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
> + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
> LTSSM_STATE_MASK;
> if (state < LTSSM_PCIE_L0) {
> debug("....PCIe link error. LTSSM=0x%02x.\n", state);
> @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie,
> struct ls_pcie_info *info)
>
> for (pf = 0; pf < PCIE_PF_NUM; pf++) {
> for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
> +#ifdef CONFIG_FSL_LAYERSCAPE
> writel(PCIE_LCTRL0_VAL(pf, vf),
> pcie->dbi + PCIE_LUT_BASE +
> PCIE_LUT_LCTRL0);
> +#endif
It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file
whose name suggests is layerscape-specific. What chips use this file that
are not CONFIG_FSL_LAYERSCAPE?
-Scott
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