[U-Boot] [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635

Kushwaha Prabhakar prabhakar at freescale.com
Thu Nov 5 04:58:56 CET 2015


> -----Original Message-----
> From: York Sun [mailto:yorksun at freescale.com]
> Sent: Thursday, November 05, 2015 12:27 AM
> To: Kushwaha Prabhakar-B32579 <prabhakar at freescale.com>; u-
> boot at lists.denx.de
> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
> 
> 
> 
> On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
> > If the core runs at higher than x3 speed of the platform, there is
> > possiblity about sev instruction to getting missed by other cores.
> > This is because of SoC Run Control block may not able to sample the
> > EVENTI(Sev) signals.
> >
> > Configure Run Control and EPU to periodically send out EVENTI signals
> > to wake up A57 cores.
> >
> > Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> > ---
> > Chages for v2: Updated description
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c           |  6 ++++
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 39
> +++++++++++++++++++++++
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 ++++++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  3 ++
> >  4 files changed, 57 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index 0cb0afa..dbb12c2 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -484,7 +484,13 @@ int arch_early_init_r(void)  {  #ifdef CONFIG_MP
> >  	int rv = 1;
> > +#endif
> > +
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> > +	erratum_a009635();
> > +#endif
> >
> > +#ifdef CONFIG_MP
> >  	rv = fsl_layerscape_wake_seconday_cores();
> >  	if (rv)
> >  		printf("Did not wake secondary cores\n");
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 637853d..e8cdb10 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -9,10 +9,49 @@
> >  #include <asm/arch/soc.h>
> >  #include <asm/io.h>
> >  #include <asm/global_data.h>
> > +#include <asm/arch-fsl-layerscape/config.h>
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> >  #ifdef CONFIG_LS2085A
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> > +#define PLATFORM_CYCLE_ENV_VAR	"a009635_interval_val"
> > +
> > +static unsigned long get_internval_val_mhz(void)
> > +{
> > +	char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
> 
> Why do you need a variable to override the calculation?
> 

Following needs to be supported as part of errata workaround
1. Ability to modify platform clock value to increase time interval
2. Disable workaround in platform clock 0

As per Errata workaround, 
 "For <interval> value above,  it is the number of platform cycles between wake up events generated by EPU.  For example: 
A typical value is 1 microsecond.  If the platform frequency is 500MHz, each cycle is 2ns. interval = 1us/2ns=500=0x1F4."

> 
> > +	ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
> 
> Please add a comment here to explain what the interval does and why it is
> calculated this way.
> 

Sure, 

--PK



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